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US4575743A Expired / Lapsed US ⏱️ 0.0 years remaining

Double layer ROM integrated circuit

Assignee: Suwa Seikosha KK
•
Filing: 1983-04-26
•
Granted: 1986-03-11
•
Expires: 2003-04-26
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Abstract

Abstract A first ROM is comprised of a transistor matrix. The polycrystalline silicon forming the gates of the transistors of the first ROM and another polycrystalline silicon region are arranged in a matrix, and diodes are formed by PN junctions at the crossing points. Thus, a second ROM is comprised of a diode matrix. The two ROMS are formed in layers on one common plane and each ROM can retain different information, independently of each other.

Inventors

  • 👤 Masami Hashimoto

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 22:07
CPC Classifications
H; H10; H10B; H10B20/00

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 85 words
A double layer ROM integrated circuit comprising: a first ROM formed of a matrix of transistors, the source, drain and gate electrodes of the transistors being formed of one of P-type and N-type polycrystalline silicon; and a second ROM formed of a matrix of diodes, the diodes being formed by a junction between P-type and N-type polycrystalline silicon regions, the gate electrodes of the transistors in the first ROM being one of the polycrystalline silicon regions forming each of the diodes in the second ROM.
Claim 2
Dependent Claim 85 words
A double layer ROM integrated circuit comprising: a first ROM formed of a matrix of transistors, the source, drain and gate electrodes of the transistors being formed of one of P-type and N-type polycrystalline silicon; and a second ROM formed of a matrix of diodes, the diodes being formed by a junction between P-type and N-type polycrystalline silicon regions, the gate electrodes of the transistors in the first ROM being one of the polycrystalline silicon regions forming each of the diodes in the second ROM.
Claim 3
Dependent Claim 25 words
The double layer ROM of claim 1 wherein the first ROM is formed of P-channel transistors, the gate electrodes being formed of P-type polycrystalline silicon.
Claim 4
Dependent Claim 35 words
The double layer ROM of claim 2 wherein the diodes of the second ROM are formed by the junctions between the P-type polycrystalline silicon gates of the first ROM transistors and N-type polycrystalline silicon regions.
Claim 5
Dependent Claim 26 words
The double layer ROM of claim 1 wherein the diode matrix forming the second ROM is formed on top of the transistors forming the first ROM.
Claim 6
Dependent Claim 30 words
The double layer ROM of claim 1 wherein each of the diodes forming the second ROM is formed on the gate of one of the transistors forming the first ROM.
Claim 7
Dependent Claim 26 words
The double layer ROM of claim 2 wherein the diode matrix forming the second ROM is formed on top of the transistors forming the first ROM.
Claim 8
Dependent Claim 26 words
The double layer ROM of claim 3 wherein the diode matrix forming the second ROM is formed on top of the transistors forming the first ROM.
Claim 9
Dependent Claim 30 words
The double layer ROM of claim 2 wherein each of the diodes forming the second ROM is formed on the gate of one of the transistors forming the first ROM.
Claim 10
Dependent Claim 30 words
The double layer ROM of claim 3 wherein each of the diodes forming the second ROM is formed on the gate of one of the transistors forming the first ROM.
Claim 11
Dependent Claim 25 words
The double layer ROM of claim 1 wherein the first ROM is formed of N-channel transistors, the gate electrodes being formed of N-type polycrystalline silicon.
Claim 12
Dependent Claim 25 words
The double layer ROM of claim 1 wherein the first ROM is formed of P-channel transistors, the gate electrodes being formed of N-type polycrystalline silicon.

References Cited (Backward Citations)

US3865651A Cited
US4041522A Cited
US4068217A Cited
US4494135A Cited
US4184085A Cited
US4180826A Cited
US4453175A Cited
US4424579A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-03-10 1989-09-09 1990-03-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-03-10 1993-09-09 1994-03-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-03-10 1997-09-09 1998-03-11 $7700.00 Window Closed / Lapsed

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