Patent US4575644A successfully refreshed from Google Patents.
US4575644A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for prevention of the metastable state in flip-flops
Assignee: Unisys Corp
•
Filing: 1983-12-02
•
Granted: 1986-03-11
•
Expires: 2003-12-02
Abstract
Abstract A synchronizing circuit using a switchable bistable element for synchronizing an asymmetric signal with the clock of a data processing system. The occurrence of a balanced or metastable state in the switchable bistable synchronizing element which can slow up the data transfer rate is inhibited by applying an asymmetric injection signal thereto having a frequency, magnitude and asymmetry such that the maintenance of a balanced or metastable state in the synchronizing element is inhibited without interfering with the normal switching operation thereof.
Inventors
- 👤 Duane W. Leslie
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:56
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/0375
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
111 words
A synchronizing circuit comprising: means providing an asynchronous input signal; means providing a clock signal; a switchable bistable element; said switchable bistable element being responsive to logical combination of said asynchronous input signal and said clock signal for providing a synchronized output signal corresponding to reception of said asynchronous input signal; and signal injection means for injecting an injection signal into said switchable bistable element in an asymmetric fashion and at a sufficiently slower rate than the reaction time of said switchable bistable element so as to inhibit maintenance of a balanced or metastable state of said switchable bistable element without interfering with normal switching operation of said switchable bistable element.
Claim 2
Dependent Claim
111 words
A synchronizing circuit comprising: means providing an asynchronous input signal; means providing a clock signal; a switchable bistable element; said switchable bistable element being responsive to logical combination of said asynchronous input signal and said clock signal for providing a synchronized output signal corresponding to reception of said asynchronous input signal; and signal injection means for injecting an injection signal into said switchable bistable element in an asymmetric fashion and at a sufficiently slower rate than the reaction time of said switchable bistable element so as to inhibit maintenance of a balanced or metastable state of said switchable bistable element without interfering with normal switching operation of said switchable bistable element.
Claim 3
Dependent Claim
32 words
The invention in accordance with claim 1, wherein said injection signal has a frequency no greater than approximately one-half of the frequency corresponding to the reaction time of said switchable bistable element.
Claim 4
Dependent Claim
15 words
The invention in accordance with claim 1, wherein said switchable bistable element is a flip-flop.
Claim 5
Dependent Claim
20 words
The invention in accordance with claim 3, wherein said signal injecting means is an oscillator providing an asymmetric output signal.
Claim 6
Dependent Claim
59 words
The invention in accordance with claim 3, wherein said flip-flop has input and output terminals comprising at least a signal input, a clock input and an output, wherein said asynchronous input signal is applied to said signal input, wherein said clock signal is applied to said clock input, and wherein said synchronized output signal is produced on said output.
Claim 7
Dependent Claim
33 words
The invention in accordance with claim 5, including another terminal in addition to said signal input, said clock input and said output, and wherein said injection signal is applied to said another terminal.
Claim 8
Dependent Claim
30 words
The invention in accordance with claim 6, wherein said another terminal is an output which provides an output signal which is inverse to the signal provided at the first-mentioned output.
Claim 9
Dependent Claim
48 words
The invention in accordance with claim 6, wherein said signal injection means includes an impedance via which said injection signal is applied to said another terminal, said impedance being chosen so that the magnitude of said injection signal does not affect the normal switching operation of said flip-flop.
Claim 10
Dependent Claim
28 words
The invention in accordance with claim 6, wherein said terminals also include a reset input for resetting said flip-flop preparatory to synchronizing a later occurring asynchronous input signal.
Claim 11
Dependent Claim
16 words
The invention in accordance with claim 5, wherein said signal injection means is a ring oscillator.
Claim 12
Independent Claim
81 words
A method for inhibiting maintenance of a balanced or metastable state in a switchable bistable synchronizing element to which a clocked asynchronous signal is applied, said method comprising injecting an injection signal into said switchable bistable element in an asymmetric fashion and at a sufficiently slower rate than the reaction time of said element such that maintenance of a balanced or metastable state of said bistable synchronizing element is inhibited without interfering with normal switching operation of said bistable switching element.
Claim 13
Independent Claim
81 words
A method for inhibiting maintenance of a balanced or metastable state in a switchable bistable synchronizing element to which a clocked asynchronous signal is applied, said method comprising injecting an injection signal into said switchable bistable element in an asymmetric fashion and at a sufficiently slower rate than the reaction time of said element such that maintenance of a balanced or metastable state of said bistable synchronizing element is inhibited without interfering with normal switching operation of said bistable switching element.
Claim 14
Dependent Claim
32 words
The invention in accordance with claim 11, wherein said injection signal has a frequency no greater than approximately one-half of the frequency corresponding to the reaction time of said bistable synchronizing element.
Claim 15
Dependent Claim
33 words
The invention in accordance with claim 11, wherein said switchable bistable synchronizing element is a flip-flop having input and output terminals, and wherein said injection signal is applied to one of said terminals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-03-10 | 1989-09-09 | 1990-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-03-10 | 1993-09-09 | 1994-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-03-10 | 1997-09-09 | 1998-03-11 | $7700.00 | Window Closed / Lapsed |