Data processing apparatus for performing high-speed arithmetic operations

Claim 2

A data processing apparatus, comprising: a central processing unit for executing a plurality of instruction codes; a data bus connected to said central processing unit; memory means, connected to said data bus, for storing data received from said central processing unit via said data bus; identification means, connected to said data bus, for identifying a predetermined instruction code from the plurality of instruction codes, the predetermined instruction code requiring said central processing unit to access said memory means; and logic operation means, connected to said data bus, said central processing unit and said identification means, for operating on data when the predetermined instruction code is identified, by receiving data from said memory means via said data bus, executing a first operation using the received data to produce data, and writing the produced data in said memory means, said logic operation means receiving, executing and writing while said central processing unit is executing a second operation as instructed by the predetermined instruction code, thereby completing the first operation in less time than said central processing unit would take to complete the first operation.

Claim 3

An apparatus as claimed in claim 1, wherein said logic operation means writes the produced data in said memory means in place of data resulting from the second operation in said central processing unit.

Claim 4

An apparatus as claimed in claim 2, wherein said logic operation means comprises means, connected to said data bus and said logic operation means, for inhibiting data resulting from the second operation in said central processing unit from being written into said memory means.

Claim 5

An apparatus as claimed in claim 1, wherein the first operation executed by said logic operation means includes an arithmetic operation on the received data from said memory means and on additional data from said central processing unit.

Claim 6

An apparatus as claimed in claim 4, wherein said logic operation means comprises: first register means, connected to said data bus, for storing the received data read by said central processing unit from said memory means; second register means, connected to said data bus, for storing the additional data from said central processing unit; and a logic operation circuit, connected to said data bus and said first and second register means, for executing the arithmetic operation on the received and additional data in said first and second register means, respectively.

Claim 7

An apparatus as claimed in claim 5, wherein said central processing unit generates a selection signal and said logic operation means further comprises a third register means, connected to said data bus and said logic operation circuit, for storing the selection signal from said central processing unit, said logic operation circuit selecting one of a plurality of arithmetic operations in dependence upon the selection signal and executing the selected arithmetic operation on the received and additional data in said first and second register means, respectively.

Claim 8

An apparatus as claimed in claim 1, wherein said central processing unit generates a selection signal and said logic operation means comprises means, connected to said data bus, for selecting one of a plurality of arithmetic operations to be executed in dependence upon the selection signal from said central processing unit.

Claim 9

An apparatus as claimed in claim 1, wherein said central processing unit executes instructions in instruction cycles and said logic operation means comprises means, connected to said central processing unit and said identification means, for producing a read data timing signal indicating when said logic operation means is to receive the received data from said memory means via said data bus and a write data timing signal indicating when said logic operation means is to write the produced data in said memory means, within one of the instruction cycles, during which the second operation corresponding to the predetermined instruction code is executed by said central processing unit.

Claim 10

A data processing apparatus, comprising: a central processing unit for executing a plurality of instruction codes; a data bus connected to said central processing unit; a video memory means, connected to said data bus, for storing data received from said central processing unit via said data bus; identification means, connected to said data bus, for identifying a predetermined instruction code from the plurality of instruction codes, the predetermined instruction code requiring said central processing unit to access said video memory means; and logic operation means, connected to said data bus, said central processing unit and said identification means, for operating on data when the predetermined instruction code is identified, by receiving data from said video memory means via said data bus, executing a first operation using the received data to product data, and writing the produced data in said video memory means, said logic operation means receiving, executing and writing while said central processing unit is executing a second operation as instructed by the predetermined instruction code, thereby completing the first operation in less time than said central processing unit would take to complete the first operation.

Claim 11

A data processing apparatus, comprising: a central processing unit for executing a plurality of instruction codes; a data bus connected to said central processing unit; a video memory means, connected to said data bus, for storing data received from said central processing unit via said data bus; identification means, connected to said data bus, for identifying a predetermined instruction code from the plurality of instruction codes, the predetermined instruction code requiring said central processing unit to access said video memory means; and logic operation means, connected to said data bus, said central processing unit and said identification means, for operating on data when the predetermined instruction code is identified, by receiving data from said video memory means via said data bus, executing a first operation using the received data to product data, and writing the produced data in said video memory means, said logic operation means receiving, executing and writing while said central processing unit is executing a second operation as instructed by the predetermined instruction code, thereby completing the first operation in less time than said central processing unit would take to complete the first operation.

Claim 12

An apparatus as claimed in claim 9, wherein said logic operation means writes the produced data in said video memory means in place of data resulting from the second operation in said central processing unit.

Claim 13

An apparatus as claimed in claim 10, wherein said logic operation means comprises means, connected to said data bus and said logic operation means, for inhibiting data resulting from the second operation in said central processing unit from being written into said video memory means.

Claim 14

An apparatus as claimed in claim 9, wherein the first operation executed by said logic operation means includes an arithmetic operation on the received data from said video memory means and on additional data from said central processing unit.

Claim 15

An apparatus as claimed in claim 12, wherein said logic operation means comprises: first register means, connected to said data bus, for storing the received data read by said central processing unit from said video memory means; second register means, connected to said data bus, for storing the additional data from said central processing unit; and a logic operation circuit, connected to said data bus and said first and second register means, for executing the arithmetic operation on the received and additional data in said first and second register means, respectively.

Claim 16

An apparatus as claimed in claim 13, wherein said central processing unit generates a selection signal and said logic operation means further comprises a third register means, connected to said data bus and said logic operation circuit, for storing the selection signal from said central processing unit, said logic operation circuit selecting one of a plurality of arithmetic operations in dependence upon the selection signal and executing the selected arithmetic operation on the received and additional data in said first and second register means, respectively.

Claim 17

An apparatus as claimed in claim 13, wherein the additional data includes image and mask data and said second register means comprises two registers, connected to said data bus, for storing the image and mask data from said central processing unit, said logic operation circuit executing an arithmetic operation on the received data stored in said first register means and the image and mask data stored in said two registers.

Claim 18

An apparatus as claimed in claim 9, wherein said central processing unit generates a selection signal and said logic operation means comprises means, connected to said data bus, for selecting one of a plurality of arithmetic operations to be executed in dependence upon the selection signal from said central processing unit.

Claim 19

An apparatus as claimed in claim 9, wherein said central processing unit executes instructions in instruction cycles and said logic operation means comprises means, connected to said central processing unit and said identification means, for producing a read data timing signal indicating when said logic operation means is to receive the received data from said video memory means via said data bus and a write data timing signal indicating when said logic operation means is to write the produced data in said video memory means, within one of the instruction cycles, during which the second operation corresponding to the predetermined instruction code is executed by said central processing unit.

Claim 20

A data processing appartus, comprising: a computer, including: a central processing unit, having an instruction set, for executing an instruction by operating on associated data to produce first resultant data; and a memory for storing the instruction, the associated data, and the first resultant data; and arithmetic means, connected to said central processing unit and said memory in said computer, for performing an arithmetic operation, not included in the instruction set of said central processing unit, during execution of the instruction, on the associated data to produce second resultant data, for suppressing storage of the first resultant data and for storing the second resultant data in the memory where said first resultant data was to be stored.

Claim 21

A data processing appartus, comprising: a computer, including: a central processing unit, having an instruction set, for executing an instruction by operating on associated data to produce first resultant data; and a memory for storing the instruction, the associated data, and the first resultant data; and arithmetic means, connected to said central processing unit and said memory in said computer, for performing an arithmetic operation, not included in the instruction set of said central processing unit, during execution of the instruction, on the associated data to produce second resultant data, for suppressing storage of the first resultant data and for storing the second resultant data in the memory where said first resultant data was to be stored.

Claim 22

A data processing apparatus, comprising: a computer, including: a central processing unit, having an instruction set for executing an instruction by operating on associated data to produce first resultant data; and a memory for storing the instruction, the associated data and the first resultant data; and arithmetic means for performing an arithmetic operation, during execution of the instruction, on the associated data to produce second resultant data, including: an address bus connected to the central processing unit and the memory; a data bus connected to the central processing unit and the memory; comparator means, connected to said data bus and the central processing unit, for identifying the instruction; timing means, connected to the central processing unit and said comparator means, for generating read data and write data timing signals indicating when the central processing unit is reading the associated data from the memory and sending the first resultant data to the memory, respectively; a first decoder connected to said address bus; a data register connected to said data bus and said timing means to receive the read data timing signal and the associated data; selection, and first and second parameter registers connected to said data bus and said first decoder; a logic operation circuit, connected to said data, selection and first and second parameter registers, for performing the arithmetic operation; a buffer, connected to said data bus, said logic operation circuit and said timing means to receive the write data timing signal, for providing the second resultant data to the memory to be stored where the first resultant data was to be stored; a first inverter connected to said timing means to receive the write data timing signal; and transfer buffers, connected to said data bus and said first inverter, for suppressing the writing of the first resultant data in dependence upon the write data timing signal as inverted by said inverter.

Claim 23

A data processing apparatus, comprising: a computer, including: a central processing unit, having an instruction set for executing an instruction by operating on associated data to produce first resultant data; and a memory for storing the instruction, the associated data and the first resultant data; and arithmetic means for performing an arithmetic operation, during execution of the instruction, on the associated data to produce second resultant data, including: an address bus connected to the central processing unit and the memory; a data bus connected to the central processing unit and the memory; comparator means, connected to said data bus and the central processing unit, for identifying the instruction; timing means, connected to the central processing unit and said comparator means, for generating read data and write data timing signals indicating when the central processing unit is reading the associated data from the memory and sending the first resultant data to the memory, respectively; a first decoder connected to said address bus; a data register connected to said data bus and said timing means to receive the read data timing signal and the associated data; selection, and first and second parameter registers connected to said data bus and said first decoder; a logic operation circuit, connected to said data, selection and first and second parameter registers, for performing the arithmetic operation; a buffer, connected to said data bus, said logic operation circuit and said timing means to receive the write data timing signal, for providing the second resultant data to the memory to be stored where the first resultant data was to be stored; a first inverter connected to said timing means to receive the write data timing signal; and transfer buffers, connected to said data bus and said first inverter, for suppressing the writing of the first resultant data in dependence upon the write data timing signal as inverted by said inverter.

Claim 24

A data processing apparatus as claimed in claim 19, wherein said comparator means comprises: a second decoder connected to the address bus; a first flip-flop connected to said decoder; a reference code setting circuit for indicating an operation code associated with the instruction; a comparator, connected to said data bus, said timing means, said first flip-flop and said reference code setting circuit, for comparing data on said data bus with the operation code.

Claim 25

A data processing apparatus as claimed in claim 20, wherein said timing means comprises: second and third inverters connected to the central processing unit; a second flip-flop connected to said second and third inverters; a third flip-flop connected to said comparator and said second flip-flop; a counter, connected to the central processing unit and said third flip-flop, for counting the clock signals generated by the central processing unit after said comparator has identified the instruction; and a timing generator, connected to said counter, said data register, said buffer and said first inverter, for generating the read data and write data timing signals.

Claim 26

A data processing apparatus as recited in claim 21, wherein the memory includes a program memory and a video memory, and said apparatus further comprises: a cathode ray tube interface circuit connected to the video memory; a multiplexer connected to the video memory and said address bus; and a cathode ray tube scanning address generator connected to said multiplexer.

Claim 27

A data processing apparatus as claimed in claim 19, wherein said logic operation circuit provides logical operations including OR, exclusive OR, AND and masking capabilities.