Cascaded CCD shift registers having different numbers of clocking phases

Claim 1

In Combination: a first CCD shift register comprising a charge transfer channel with input and output ends and a plurality of gate electrodes crossing over said charge transfer channel, said gate electrodes consecutively ordinally numbered first through m th within consecutive cycles of m successive gate electrodes, from input to output ends of the charge transfer channel of said first CCD shift register, m being a positive integer greater than another positive integer n; a second CCD shift register comprising a charge transfer channel with input and output ends and a plurality of gate electrodes crossing over said charge transfer channel, said gate electrodes consecutively ordinally numbered first through n th within consecutive cycles of n successive gate electrodes, from input to output ends of the charge transfer channel of said second CCD shift register; a connection of the output end of the charge transfer channel of said first CCD shift register to the input end of the charge transfer channel of said CCD shift register; and means for generating first and second clocking signals of the same periodicity, said first clocking signal having m phases ordinally numbered first through m th respectively applied to gate electrodes of said first CCD register having the same ordinal numbering as the phase so applied, said second clocking signal having n phases ordinally numbered first through n th respectively applied to gate electrodes of said second CCD register having the same ordinal numbering as the phase so applied, selected phases of said first and second clocking voltages being arranged to overlap in time in such phasing as to avoid merger of successive charge packets at said connection of the output end of the charge transfer channel of said first CCD shift register to the input end of the charge transfer channel of said second shift register.