Reducing grain in multi-phase-clocked CCD imagers

Claim 1

A method for biasing during at least selected image integration times the gate electrodes in a CCD imager register to reduce the grain in the CCD imager output signal, said register being of the type with gate electrodes arranged in successive cycles of a first-phase gate electrode followed by a second-phase-gate electrode followed by a third-phase gate electrode, clocked three-phase during image transfer times, said method comprising the steps of during those at least selected image integration times: applying first bias potential to said second-phase electrodes and applying second bias potential to said third-phase electrodes, one of said first and second bias potentials being of a value for inducing charge carrier collection sites close by the gate electrodes to which it is applied, for collecting charge carriers generated in said register, and the other of said first and second bias potentials being of a value not to induce charge carrier collection sites; and applying to said first-phase electrodes a third bias potential intermediate between said first and second bias potentials, sufficiently offset from said other of said first and second bias potentials to substantially reduce the grain in the CCD imager output signal.

Claim 2

A method for biasing during at least selected image integration times the gate electrodes in a CCD imager register to reduce the grain in the CCD imager output signal, said register being of the type with gate electrodes arranged in successive cycles of a first-phase gate electrode followed by a second-phase-gate electrode followed by a third-phase gate electrode, clocked three-phase during image transfer times, said method comprising the steps of during those at least selected image integration times: applying first bias potential to said second-phase electrodes and applying second bias potential to said third-phase electrodes, one of said first and second bias potentials being of a value for inducing charge carrier collection sites close by the gate electrodes to which it is applied, for collecting charge carriers generated in said register, and the other of said first and second bias potentials being of a value not to induce charge carrier collection sites; and applying to said first-phase electrodes a third bias potential intermediate between said first and second bias potentials, sufficiently offset from said other of said first and second bias potentials to substantially reduce the grain in the CCD imager output signal.

Claim 4

A method for biasing the gate electrodes in the image register of a CCD imager of field transfer type during field integration times, which image register is of the type clocked three-phase during field transfer times, said method comprising the steps of: during field integration times in alternate fields biasing the second-phase gate electrodes with a relatively high bias potential and the third-phase gate electrodes with a relatively low bias potential; during field integration times in the intervening fields biasing the third-phase gate electrodes with a relatively high bias potential and the second-phase gate electrodes with a relatively low bias potential; and during all field integration times biasing the first-phase gate electrodes with an intermediate bias potential between the relatively high and low bias potentials, said intermediate bias being more than relatively low in at least such degree as to reduce grain to be appreciably close to its minimum.

Claim 5

A method for biasing the gate electrodes in the image register of a CCD imager of field transfer type during field integration times, which image register is of the type clocked three-phase during field transfer times, said method comprising the steps of: during field integration times in alternate fields biasing the second-phase gate electrodes with a relatively high bias potential and the third-phase gate electrodes with a relatively low bias potential; during field integration times in the intervening fields biasing the third-phase gate electrodes with a relatively high bias potential and the second-phase gate electrodes with a relatively low bias potential; and during all field integration times biasing the first-phase gate electrodes with an intermediate bias potential between the relatively high and low bias potentials, said intermediate bias being more than relatively low in at least such degree as to reduce grain to be appreciably close to its minimum.

Claim 11

A method for reducing grain in the output of a CCD imager of the type having an image register to which three-phase clocking signals are applied during times of field transfer, said method comprising during each image integration time between successive field transfer times performing the steps of: applying to every third gate electrode a bias voltage for inducing proximate to that electrode a potential well for collecting charge carriers; and applying to each intervening pair of gate electrodes respective bias voltages for causing a stepped potential barrier, with one step being proximate to one gate electrode of the pair and the other step proximate to the other gate electrode of the pair.

Claim 12

A method for reducing grain in the output of a CCD imager of the type having an image register to which three-phase clocking signals are applied during times of field transfer, said method comprising during each image integration time between successive field transfer times performing the steps of: applying to every third gate electrode a bias voltage for inducing proximate to that electrode a potential well for collecting charge carriers; and applying to each intervening pair of gate electrodes respective bias voltages for causing a stepped potential barrier, with one step being proximate to one gate electrode of the pair and the other step proximate to the other gate electrode of the pair.