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US4573120A Expired / Lapsed US ⏱️ 0.0 years remaining

I/O Control system for data transmission and reception between central processor and I/O units

Assignee: Advantest Corp
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Filing: 1983-11-01
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Granted: 1986-02-25
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Expires: 2003-11-01
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Abstract

Abstract A central processing unit is cascade-connected with a plurality of I/O units, and a bus interconnecting them comprises a plurality of data lines for transmitting a control command signal, an address signal and a data signal on a time shared basis, a plurality of tag lines, each transmitting a tag signal indicating which one of the signals is provided on the data lines, and a clock line for transmitting a clock signal for these signals.

Inventors

  • 👤 Yoshichika Ichimiya
  • 👤 Tsuneta Sudo
  • 👤 Turo Takehisa
  • 👤 Katsumi Shimada

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 06:01
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4247

Claims Analysis

Total Claims: 17
Claim 1
Independent Claim 279 words
An I/O control system comprising: a central processing unit with input and output ports for respectively transmitting and receiving control commands and data; a plurality of I/O units, each for performing data transmission and reception between it and the central processing unit in accordance with said control commands from the central processing unit, and each having an input port and an output port; and a transmission bus for cascade connecting said input and output ports of said I/O units with each other and with said input and output ports of the central processing unit, the bus comprising a plurality of one-way data lines for transmitting on a time shared basis a control command signal for providing each said control command, an address signal for selecting each respective I/O unit and respective data signal, a plurality of tag lines for transmitting a respective tag signals indicating which of said control command, address and data signals is being sent out on the data lines, and a clock line for transmitting a reference clock signal in correspondence with said control command, address, data and tag signals; wherein said one-way transmission bus includes a respective segment connecting internally between the input and output ports of each said I/O unit, each said input port of each said I/O unit includes a respective receiver for each of said data, tag and clock lines, each said output port of each said I/O unit includes a respective driver for each of said data, tag and clock lines, and the output of each said receiver is connected to the input of the respective driver for each of said data, tag and clock lines of each respective I/O unit.
Claim 2
Dependent Claim 279 words
An I/O control system comprising: a central processing unit with input and output ports for respectively transmitting and receiving control commands and data; a plurality of I/O units, each for performing data transmission and reception between it and the central processing unit in accordance with said control commands from the central processing unit, and each having an input port and an output port; and a transmission bus for cascade connecting said input and output ports of said I/O units with each other and with said input and output ports of the central processing unit, the bus comprising a plurality of one-way data lines for transmitting on a time shared basis a control command signal for providing each said control command, an address signal for selecting each respective I/O unit and respective data signal, a plurality of tag lines for transmitting a respective tag signals indicating which of said control command, address and data signals is being sent out on the data lines, and a clock line for transmitting a reference clock signal in correspondence with said control command, address, data and tag signals; wherein said one-way transmission bus includes a respective segment connecting internally between the input and output ports of each said I/O unit, each said input port of each said I/O unit includes a respective receiver for each of said data, tag and clock lines, each said output port of each said I/O unit includes a respective driver for each of said data, tag and clock lines, and the output of each said receiver is connected to the input of the respective driver for each of said data, tag and clock lines of each respective I/O unit.
Claim 3
Independent Claim 65 words
The system of 1, wherein the central processing unit is provided with means for sending out the control command signal, the address signal and the data signal on the data lines in synchronism with the clock signal on the time shared basis, and means for sending out on the tag lines the tag signal indicating the kind of signal sent out on the data lines.
Claim 4
Independent Claim 65 words
The system of 1, wherein the central processing unit is provided with means for sending out the control command signal, the address signal and the data signal on the data lines in synchronism with the clock signal on the time shared basis, and means for sending out on the tag lines the tag signal indicating the kind of signal sent out on the data lines.
Claim 5
Dependent Claim 73 words
The system of claim 1 or 2, wherein each said I/O unit includes a means for providing to said segment of each said data line a data signal read out from the respective I/O unit in response to a read-out command from said central processing unit, and for providing to the segment of each corresponding tag line a data indicating signal indicating the sending out of the data signal by the I/O unit.
Claim 6
Dependent Claim 178 words
The system of claim 1 or 2, wherein each said I/O unit includes a control command register which is controlled by a respective control command indicating signal on each respective one of said tag lines and the clock signal on the clock lines from the respective input port, to latch the respective control command signal on each respective data line from the input port, a control command decoder for decoding the content of the control command register, an address register for controlling the address signal of the data lines from the input port by the address indicating signal of the tag lines and the clock signal of the clock line to latch the address signal, an address decoder for detecting whether the content of the address register corresponds to the address of the respective I/O unit, and a data register controlled by the output from the address decoder, a write command output from the control command decoder, the data indicating signal of the tag lines and the clock signal to latch the data signal of the data lines.
Claim 7
Dependent Claim 77 words
The I/O system of claim 4, each said I/O unit including means for outputting said data signal from the I/O unit via the output port in correspondence with said detected output from the respective address decoder, said data read-out output from the control command decoder and the clock signal, and means for sending out a corresponding data sending out indicating signal via the output port to a respective tag line during the sending out of the data.
Claim 8
Dependent Claim 57 words
The I/O system of claim 1 or 2, each said I/O unit including means for detecting the respective address signal for the I/O unit and generating a respective response signal, and said bus including a response signal line for transmitting the response signal from each I/O unit to said central processing unit by a respective cascade connection.
Claim 9
Dependent Claim 31 words
The system of claim 6, wherein the direction of signal transmission of the response signal line is opposite to said common direction of transmission on the data, tag and clock lines.
Claim 10
Dependent Claim 25 words
The system of claim 1 or 2, wherein a respective one of said tag lines is provided in correspondence to each of said indicating signals.
Claim 11
Dependent Claim 63 words
The I/O system of claim 1 or 2, wherein the number of said tag lines is smaller than the number of kinds of said control command, address and data signals transmitted over said data lines, and wherein said command control, address and data signals on said data lines are identified as such by respective combinations of signals on the plurality of tag lines.
Claim 12
Dependent Claim 31 words
The I/O system of claim 1 or 2, wherein each said I/O unit is provided with re-timing means for synchronously timing the signals output from the drivers of the I/O unit.
Claim 13
Dependent Claim 35 words
The system of claim 7, said response signal line including a receiver and a driver in each said I/O unit, wherein a signal corresponding to the output of the receiver is input into the driver.
Claim 14
Dependent Claim 28 words
The system of claim 11, wherein each said I/O unit is provided with re-timing means for synchronously timing the signals output from the drivers of the I/O unit.
Claim 15
Dependent Claim 31 words
The system of claim 1 or 2, said drivers and receivers of each said I/O unit being powered independently from the supply of power to other components of the I/O unit.
Claim 16
Dependent Claim 28 words
The system of claim 3, wherein each said I/O unit is provided with re-timing means for synchronously timing the signals output from the drivers of the I/O unit.
Claim 17
Dependent Claim 34 words
The system o claim 1 or 2 wherein each said I/O uit includes an interface unit which comprises each said internal segment of said one-way transmission bus, driver and receiver of the I/O unit.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-02-24 1989-08-26 1990-02-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-02-24 1993-08-26 1994-02-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-02-24 1997-08-26 1998-02-25 $7700.00 Window Closed / Lapsed

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