Patent US4573038A successfully refreshed from Google Patents.
US4573038A
Expired / Lapsed
US
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Linear codec with dual divider
Assignee: AT&T Inc
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Filing: 1984-02-23
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Granted: 1986-02-25
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Expires: 2004-02-23
Abstract
Abstract Disclosed is a charge redistribution codec employing a two capacitor network for developing a progression of reference voltages having a binary relationship to each other for each analog input sample to be encoded. Linear encoding of input samples is achieved with the use of two such charge redistribution networks, with one developing positive reference voltages and the other developing negative reference voltages. Analog input samples are placed in an encoding capacitor and based on the polarity of the voltage across the capacitor either a positive or a negative charge is added iteratively to the capacitor in the direction of driving the voltage across that capacitor to zero. A code is developed by assigning at each iteration one value to an output code bit when a positive voltage is added and the opposite value to the bit when a negative voltage is added. Chord-law encoding is achieved in a similar manner except that the output code includes a sign bit, a chord count and a linear code for describing the signal within the chord. Operationally, as with linear encoding two reference voltage generating circuits are employed to provide the positive and negative reference voltages. In addition, means are provided for adding an offset voltage to increase the magnitude of the input sample for assigning a sign bit based on the initial polarity of the input sample and for chord counting.
Inventors
- 👤 Robert L. Carbrey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 14:49
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/02; H03M1/12; H03M1/34; H03M1/38; H03M1/40; H03M1/66; H03M1/74
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
228 words
A binary reference voltage generator for iteratively developing a progression of reference voltages with each reference voltage being one half the previous voltage comprising: a first source capacitor for storing charges; a first reference-charge capacitor; first switch means for distributing the charges of said first source capacitor between said first source capacitor and said first reference-charge capacitor; second switch means for discharging said first reference-switch capacitor; third switch means for accessing and drawing the charge of said first reference-charge capacitor; fourth switch means for charging said first source capacitor at the beginning of each progression; first means for cyclically turning on and off said first and second switch means during each iteration; means for applying a positive maximum reference voltage to said first source capacitor; a second source capacitor for storing charges; a second reference-charge capacitor; fifth switch means for distributing the charges of said second source capacitor between said second source capacitor and said second reference-charge capacitor; sixth switch means for discharging said second reference-charge capacitor; seventh switch means for accessing and drawing the charge of said second reference-charge capacitor; eighth switch means for charging said second source capacitor; second means for cyclically turning on and off said fifth and sixth switch means; and second means for applying a negative maximum reference voltage to said second source capacitor, equal in magnitude to said positive maximum reference voltage.
Claim 2
Dependent Claim
228 words
A binary reference voltage generator for iteratively developing a progression of reference voltages with each reference voltage being one half the previous voltage comprising: a first source capacitor for storing charges; a first reference-charge capacitor; first switch means for distributing the charges of said first source capacitor between said first source capacitor and said first reference-charge capacitor; second switch means for discharging said first reference-switch capacitor; third switch means for accessing and drawing the charge of said first reference-charge capacitor; fourth switch means for charging said first source capacitor at the beginning of each progression; first means for cyclically turning on and off said first and second switch means during each iteration; means for applying a positive maximum reference voltage to said first source capacitor; a second source capacitor for storing charges; a second reference-charge capacitor; fifth switch means for distributing the charges of said second source capacitor between said second source capacitor and said second reference-charge capacitor; sixth switch means for discharging said second reference-charge capacitor; seventh switch means for accessing and drawing the charge of said second reference-charge capacitor; eighth switch means for charging said second source capacitor; second means for cyclically turning on and off said fifth and sixth switch means; and second means for applying a negative maximum reference voltage to said second source capacitor, equal in magnitude to said positive maximum reference voltage.
Claim 3
Dependent Claim
151 words
The apparatus of claim 1, further comprising: means for sampling an applied analog signal at a predetermined sampling rate and placing developed analog samples on an encoding capacitor; means for adding to said encoding capacitor at each iteration of said reference voltage generator the developed reference voltage of said first reference-charge capacitor when the polarity of voltage across said encoding capacitor is negative; means for adding to said encoding capacitor at each iteration of said reference voltage generator the developed reference voltage of said second reference-charge capacitor when the polarity of voltage across said encoding capacitor is positive; and means for developing at each iteration of said reference-voltage generator an output bit of said encoder which is at one binary state when the polarity of voltage across said encoding capacitor is negative and which is at a second binary state when the polarity of voltage across said encoding capacitor is positive.
Claim 4
Dependent Claim
91 words
The apparatus of claim 1, responsive to a linearly encoded applied digital signal comprising bits having a first state and a second state and further comprising: an output capacitor for storing an output voltage; and means, responsive to each bit of said applied digital signal for adding to the voltage of said output capacitor a reference voltage of said first reference-charge capacitor in response to said first state of said each bit, or a reference voltage of said second reference-charge capacitor in response to said second state of said each bit.
Claim 5
Dependent Claim
147 words
Apparatus of claim 2 further comprising: means for determining the initial polarity of voltage across said encoding capacitor at commencement of each of said progressions and assigning a sign bit value based on said polarity; means for increasing the magnitude of said analog samples by a preselected offset; means for incrementing a chord count with each iteration of said reference voltage generator following assignment of said sign bit until the polarity of voltage across said encoding capacitor equals said polarity at time of sign bit assignment; and means for developing at each iteration following completion of said chord count, for a fixed number of iterations, an output bit of said encoder which is at one binary state when a reference voltage of said first reference-charge capacitor is added and which is at a second binary state when a reference voltage of said second reference-charge capacitor is added.
Claim 6
Dependent Claim
152 words
Apparatus of claim 1 further comprising: means for placing on a capacitor an offset voltage having a polarity determined by the sign bit of a periodically applied chord-law encoded digital representation of sampled analog signals that includes a chord count and a linear code as well as the sign bit; means for decrementing with each iteration of said reference voltage generator said chord count by one until said chord count reaches zero; means for adding to said capacitor during chord count decrementing reference voltages of said first or second reference-charge capacitors based on the value of said sign bit; and means for adding to said capacitor, following said chord count decrementing, reference voltages of said first reference-charge capacitor in response to one state of corresponding bits in said linear count and adding reference voltages of said second reference-charge capacitor in response to the second state of corresponding bits in said linear count.
References Cited (Backward Citations)
US3449741A
Cited
US3469255A
Cited
FR1593686A
Cited
US3626408A
Cited
US4291298A
Cited
US4185275A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-24 | 1989-08-26 | 1990-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-24 | 1993-08-26 | 1994-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-24 | 1997-08-26 | 1998-02-25 | $7700.00 | Window Closed / Lapsed |