Patent US4573036A successfully refreshed from Google Patents.
US4573036A
Expired / Lapsed
US
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Integrable circuit for digital-to-analog converter
Assignee: Siemens AG
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Filing: 1982-12-09
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Granted: 1986-02-25
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Expires: 2002-12-09
Abstract
Abstract Integrable circuit for digital/analog converters wherein individual signal inputs addressed by part of a digital signal to be processed are connected to the same first terminal of a respective first diode, the first diode having a second terminal connected to the same terminal of a respective second diode and, furthermore, connected to an output of a transistor operated as a current source, the second diode of the diode pairs controlled by the individual signal inputs having a second terminal for jointly controlling an output amplifier, wherein the original current source transistors have respective current-carrying inputs addressed, via a respective resistor, by a common supply terminal, and wherein the individual diode pairs are mutually identical, and the current source transistors are of the same type, comprising at least one second current source transistor operatively associated with each of the first-mentioned current source transistors, both of said first mentioned and said second source transistors having current input electrodes, respectively, directly connected to one another, and current output electrodes of respective mutually associated pairs of said first-mentioned and said second current source transistors connected to a respective one of two identical digitally controlled circuit parts forming, together with resistances connected to said current input electrodes of the respective current source transistors, respective analog/digital converters.
Inventors
- 👤 Jurgen Wondra
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 19:58
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/74
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
266 words
In an integrable digital/analog converter arrangement including at least two digital/analog converter circuits each including: a plurality of inputs for a digital input signal to be converted into an analog output signal, said inputs corresponding in number to the number of bits of said digital input signal, a plurality of first diodes each connected with a first terminal to a corresponding one of said inputs, an equal plurality of second diodes which are mutually identical with said first diodes, a second terminal of each of said first diodes being connected to a second terminal of a corresponding one of said second diodes and the first terminals of said second diodes being commonly connected to an input of an output amplifier for providing said analog output signal, and a plurality of digitally weighted current sources each comprising a current source transistor, said transistors all being of the same type, and a plurality of resistors each having first and second terminals, wherein current input terminal of each one of said current source transistors are respectively connected to the first terminal of the corresponding one of said resistors, the second terminals of said resistors being commonly connected to a common power supply terminal, and the current output terminals of said current source transistors being connected to corresponding second terminals of said first diodes and to corresponding second terminals of said second diodes, the improvement comprising that said current input terminals of the corresponding current source transistors of said at least two digital/analog converter circuits are commonly connected to said power supply terminal via a corresponding one of said resistors.
Claim 2
Dependent Claim
266 words
In an integrable digital/analog converter arrangement including at least two digital/analog converter circuits each including: a plurality of inputs for a digital input signal to be converted into an analog output signal, said inputs corresponding in number to the number of bits of said digital input signal, a plurality of first diodes each connected with a first terminal to a corresponding one of said inputs, an equal plurality of second diodes which are mutually identical with said first diodes, a second terminal of each of said first diodes being connected to a second terminal of a corresponding one of said second diodes and the first terminals of said second diodes being commonly connected to an input of an output amplifier for providing said analog output signal, and a plurality of digitally weighted current sources each comprising a current source transistor, said transistors all being of the same type, and a plurality of resistors each having first and second terminals, wherein current input terminal of each one of said current source transistors are respectively connected to the first terminal of the corresponding one of said resistors, the second terminals of said resistors being commonly connected to a common power supply terminal, and the current output terminals of said current source transistors being connected to corresponding second terminals of said first diodes and to corresponding second terminals of said second diodes, the improvement comprising that said current input terminals of the corresponding current source transistors of said at least two digital/analog converter circuits are commonly connected to said power supply terminal via a corresponding one of said resistors.
Claim 3
Dependent Claim
33 words
Integrable digital/analog converter arrangement according to claim 1 comprising a further transistor having its base commonly connected to the bases of said plurality of current source transistors to form current mirror current sources.
Claim 4
Dependent Claim
88 words
Integrable digital/analog converter arrangement according to claim 1 wherein said current source transistors comprising bipolar transistors each having a base, an emitter, and a plurality of collectors wherein the number of said collectors corresponds to the number of said digital/analog converter circuits and wherein said emitters of said bipolar transistors are coupled by said resistors to said common power supply terminals and wherein said collectors of said bipolar transistors are coupled to said commonly connected first terminals of said first and second diodes of corresponding digital/analog converter circuits.
Claim 5
Dependent Claim
51 words
Integrable digital/analog converter arrangement according to claim 3, wherein said first and second diodes comprise bipolar transistors each having a base, a collector and two emitters and wherein said base and said collector are directly connected and wherein said emitter forms said second terminals of said first and second diodes, respectively.
Claim 6
Dependent Claim
16 words
Integrable digital/analog converter arrangement according to claim 1 wherein said output amplifier comprises an operational amplifier.
Claim 7
Dependent Claim
27 words
Integrable digital/analog converter arrangement according to claim 4 wherein said two-emitter transistor is of a conductivity type opposite to the conductivity type of said current source transistors.
Claim 8
Dependent Claim
25 words
Integrable digital/analog converter arrangement according to claim 3 wherein said resistors connecting said current source transistors and said common supply potential form an R-2R network.
Claim 9
Dependent Claim
29 words
Integrable digital/analog converter arrangement according to claim 1 wherein each of the respective converters are connected to a respective operational amplifier with negative feedback serving as said output amplifier.
Claim 10
Dependent Claim
30 words
Integrable digital/analog converter arrangement according to claim 7 including a respective inverter for digitally controlling individual sign inputs of said converters, said converters being mutually connected via said R-2R network.
Claim 11
Dependent Claim
25 words
Integrable digital/analog converter arrangement according to claim 1 wherein the current input terminals of the current source transistors respective of each converter are commonly connected.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-24 | 1989-08-26 | 1990-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-24 | 1993-08-26 | 1994-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-24 | 1997-08-26 | 1998-02-25 | $7700.00 | Window Closed / Lapsed |