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US4571507A
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Successive approximation analog-to-digital converter
Assignee: Sipex Corp
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Filing: 1982-05-12
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Granted: 1986-02-18
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Expires: 2002-05-12
Abstract
Abstract A successive approximation analog-to-digital converter utilizes an improved high-gain current comparator having a zero input impedance characteristic in combination with an equal current digital-to-analog converter. The zero input impedance comparator permits the use of low power C-MOS switching circuitry by leading the output of the digital-to-analog converter to the zero impedance input of the comparator, thereby overcoming the problem of decreased switching speed associated with high capacitance C-MOS outputs. The zero impedance current comparator includes an improved current-to-voltage converter having an overdrive shunt circuit to reduce quiescent current and to permit higher value load resistors for better gain; and cascaded current cells to provide increased gain.
Inventors
- 👤 Jerry M. Collings
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:53
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/22; H03K5/24; H03K5/2409; H03K5/2418; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38; H03M1/40; H03M1/46
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
186 words
A zero input impedance current comparator comprising: a zero impedance current-to-voltage converter and a voltage comparator, said converter including a first pair of transistors having collectors and having interconnected bases, load resistors coupled between the collectors of respective transistors of said first pair of transistors and a positive voltage source, means for providing a voltage to the bases of said first pair of transistors such that the emitter of one of said first pair of transistors is driven to zero responsive to the voltage at the emitter of said one transistor, means adapted to apply an input signal to the emitter of the other of said transistors, and current shunt means coupled between said emitters and a negative voltage source so as to shunt therethrough increased currents responsive to increased currents through said one transistor, said means for providing a voltage to the bases of said first pair of transistors further including means for controlling said shunt means responsive to said increased currents through said one transistor, said voltage comparator having input terminals coupled to different ones of said collectors of said first pair of transistors.
Claim 2
Dependent Claim
186 words
A zero input impedance current comparator comprising: a zero impedance current-to-voltage converter and a voltage comparator, said converter including a first pair of transistors having collectors and having interconnected bases, load resistors coupled between the collectors of respective transistors of said first pair of transistors and a positive voltage source, means for providing a voltage to the bases of said first pair of transistors such that the emitter of one of said first pair of transistors is driven to zero responsive to the voltage at the emitter of said one transistor, means adapted to apply an input signal to the emitter of the other of said transistors, and current shunt means coupled between said emitters and a negative voltage source so as to shunt therethrough increased currents responsive to increased currents through said one transistor, said means for providing a voltage to the bases of said first pair of transistors further including means for controlling said shunt means responsive to said increased currents through said one transistor, said voltage comparator having input terminals coupled to different ones of said collectors of said first pair of transistors.
Claim 3
Dependent Claim
27 words
The comparator of claim 1 wherein said converter includes a current source and at least one differential gain stage coupled between said emitters and said current source.
Claim 4
Dependent Claim
52 words
The comparator of claim 2 wherein said differential gain stage includes a second pair of transistors having respective bases coupled to the emitters of corresponding transistors of said first pair, having respective collectors coupled to the collectors of different transistors of said first pair, and having emitters coupled to said current source.
References Cited (Backward Citations)
US4147943A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-17 | 1989-08-19 | 1990-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-17 | 1993-08-19 | 1994-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-17 | 1997-08-19 | 1998-02-18 | $7700.00 | Window Closed / Lapsed |