Patent US4570222A successfully refreshed from Google Patents.
US4570222A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Information processor having information correcting function
Assignee: NEC Electronics Corp
•
Filing: 1983-09-06
•
Granted: 1986-02-11
•
Expires: 2003-09-06
Abstract
Abstract The invention selectively designates a specific portion of information which is stored in a memory to identify information which is to be corrected. It further enables a correction of only the suitably designated portion. The read out of information having the corrected information is set in a state which is ready for use. Accordingly, it is not necessary to use a bit addressing circuit, as used in the prior art, this simplifying both the circuit design and the wiring. It is also possible to designate more than one arbitrary item of information as portions which are to be corrected and then to correct all designated information simultaneously. Thus, the read out information is corrected at a high speed. In addition, the number of information items which are capable of correction is not limited by unnecessary bit addressing. This enables an increase in the number of memory elements, and makes the system quite useful as a control device for CRT display systems.
Inventors
- 👤 Tetsuji Oguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-10 02:23
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/04; G09; G09G; G09G1/00; G09G1/02
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
297 words
An information processor comprising memory means storing information comprising a plurality of words, each of said stored words having a plurality of bits, means for generating address data to designate one of said stored words, means coupled to said memory means and to said generating means for applying said address data to said memory means, means coupled to said memory means and responsive to said address data for taking a plurality of bits, in parallel, out of said memory means, the plurality of bits taken out of said memory means being one word designated by each of said address data, designating means for designating at least one of the taken-out plurality of bits, a changing means for each of the plurality of bits, said changing means comprising an inverter, changing gate and transferring gate, the inverter being coupled to said taking out means for inverting and changing the associated bit from said taking out means, the changing gate being coupled to said inverter and to the designating means for transferring the associated changed bit only if the bit is one of the at least one designated bits and the transferring gate being coupled to said taking out means and to the designating means for transferring the associated bit without change if the bit is not one of the at least one designated bits, and writing means coupled to said changing means and to said memory means for simultaneously writing said at least one changed bit and unchanged bits into the same address of said memory means as the address from which said plurality of bits have been taken out, the word length of said at least on changed bit and unchanged bits being equal to that of the taken out plurality of bits of said one word.
Claim 2
Dependent Claim
297 words
An information processor comprising memory means storing information comprising a plurality of words, each of said stored words having a plurality of bits, means for generating address data to designate one of said stored words, means coupled to said memory means and to said generating means for applying said address data to said memory means, means coupled to said memory means and responsive to said address data for taking a plurality of bits, in parallel, out of said memory means, the plurality of bits taken out of said memory means being one word designated by each of said address data, designating means for designating at least one of the taken-out plurality of bits, a changing means for each of the plurality of bits, said changing means comprising an inverter, changing gate and transferring gate, the inverter being coupled to said taking out means for inverting and changing the associated bit from said taking out means, the changing gate being coupled to said inverter and to the designating means for transferring the associated changed bit only if the bit is one of the at least one designated bits and the transferring gate being coupled to said taking out means and to the designating means for transferring the associated bit without change if the bit is not one of the at least one designated bits, and writing means coupled to said changing means and to said memory means for simultaneously writing said at least one changed bit and unchanged bits into the same address of said memory means as the address from which said plurality of bits have been taken out, the word length of said at least on changed bit and unchanged bits being equal to that of the taken out plurality of bits of said one word.
Claim 3
Dependent Claim
27 words
An information processor claimed in claim 1, wherein said changing gate operates to make the logic signal of said at least one designated bit the logic "0".
Claim 4
Dependent Claim
61 words
The information processor claimed in claim 2, wherein said changing means has a designation signal input section, a taken out information input section, a changing section and a passing section, said first designation signal and said second designation signal being applied to said designation signal input section, and said taken out information being applied to said taken out information input section.
Claim 5
Dependent Claim
33 words
The information processor claimed in claim 3, wherein said changing section is activated in response to said first designation signal, and said passing section is activated in response to said second designation signal.
Claim 6
Dependent Claim
67 words
An information processor claimed in claim 1, wherein each of said changing gates is made conductive in response to an application thereto of an output signal from said designating means, to pass the changed bit to said writing means, or each of said transferring gates is made conductive in response to the output signal of said designating means to pass the unchanged bit from said taking-out means.
Claim 7
Dependent Claim
20 words
The information processor claimed in claim 1, wherein each of the bits has a logical state of "1" or "0".
Claim 8
Dependent Claim
31 words
The information processor claimed in claim 1, wherein said transferring gate is disenabled when said designating means identifies all of said taken out bits as bits which are to be changed.
Claim 9
Dependent Claim
150 words
An information processor comprising: a random access memory means having a plurality of addressed memory locations for storing information therein; means for simultaneously reading out a plurality of the stored information from the addressed memory locations of said random access memory means; changing means having two inverting circuits, a setting circuit, a resetting circuit, and a replacing circuit, said replacing circuit in said changing means replacing said read out information by new information; selecting means coupled to said changing means for selecting one of said two inverting circuits in response to a command signal; designating means coupled to said changing means for designating at least one of said plurality of read out information; said changing means changing said designated information by means of the circuit selected by said selecting means; and means for simultaneously restoring said changed information and any non-changed read out information to said random access memory means.
Claim 10
Dependent Claim
150 words
An information processor comprising: a random access memory means having a plurality of addressed memory locations for storing information therein; means for simultaneously reading out a plurality of the stored information from the addressed memory locations of said random access memory means; changing means having two inverting circuits, a setting circuit, a resetting circuit, and a replacing circuit, said replacing circuit in said changing means replacing said read out information by new information; selecting means coupled to said changing means for selecting one of said two inverting circuits in response to a command signal; designating means coupled to said changing means for designating at least one of said plurality of read out information; said changing means changing said designated information by means of the circuit selected by said selecting means; and means for simultaneously restoring said changed information and any non-changed read out information to said random access memory means.
References Cited (Backward Citations)
US2552629A
Cited
US3402390A
Cited
US4016544A
Cited
US4203102A
Cited
US4149184A
Cited
US4296494A
Cited
US4290063A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-10 | 1989-08-12 | 1990-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-10 | 1993-08-12 | 1994-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-10 | 1997-08-12 | 1998-02-11 | $7700.00 | Window Closed / Lapsed |