US4570218A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for the detection of programmable stop codes
Assignee: Individual
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Filing: 1983-07-08
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Granted: 1986-02-11
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Expires: 2003-07-08
Abstract
Abstract A system for the detection of programmable stop codes in a data exchange performed between the local memory of a microprocessor and the peripheral unit in a microprocessor assembly using direct access circuit to the local memory. This circuit divides the access to a common bus permitting data exchanges between a peripheral unit and the local memory. The system comprises a random access memory receiving the data on addressing inputs and receiving an address bit on a data input, a control circuit having outputs which are respectively connected to validation and writing control inputs of the random access memory. The control circuit repectively receives on inputs, signals coming from the microprocessor or the direct access circuit and which respectively relate to the writing or reading input-output operations as well as to the address decoding of the data. The system also comprises a test circuit connected to a reading output of the random access memory for testing during the data exchange a binary value recorded at the current address of the random access memory and representing the presence of the absence of a stop code in the data.
Inventors
- 👤 Pierre Debesson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:52
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/285
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
228 words
A system for the detection of programmable stop codes in a data exchange performed between a local memory of each microprocessor of a microprocessor assembly and at least a peripheral unit, each microprocessor being connected to a direct access circuit to the local memory, said circuit also dividing the access to a common bus permitting data exchanges between the peripheral unit and the local memory, the system comprising a random access memory having addressing inputs receiving data and a data input receiving an address bit, a control circuit having outputs which are respectively connected to validation and writing control inputs of the random access memory, whereby said control circuit respectively receives on inputs signals coming from the microprocessor or the direct access circuit and which respectively relate to writing or reading input-output operations of the peripheral unit, as well as to address decoding of the data, and a test circuit connected to a reading output of the random access memory for testing during a data exchange a binary value recorded at a current address of the random access memory and determined by the data, said testing being controlled by a test control signal applied to the test circuit by the direct access circuit to the local memory of the microprocessor, the binary value being representative of the presence or the absence of a stop code in the data.
Claim 2
Independent Claim
228 words
A system for the detection of programmable stop codes in a data exchange performed between a local memory of each microprocessor of a microprocessor assembly and at least a peripheral unit, each microprocessor being connected to a direct access circuit to the local memory, said circuit also dividing the access to a common bus permitting data exchanges between the peripheral unit and the local memory, the system comprising a random access memory having addressing inputs receiving data and a data input receiving an address bit, a control circuit having outputs which are respectively connected to validation and writing control inputs of the random access memory, whereby said control circuit respectively receives on inputs signals coming from the microprocessor or the direct access circuit and which respectively relate to writing or reading input-output operations of the peripheral unit, as well as to address decoding of the data, and a test circuit connected to a reading output of the random access memory for testing during a data exchange a binary value recorded at a current address of the random access memory and determined by the data, said testing being controlled by a test control signal applied to the test circuit by the direct access circuit to the local memory of the microprocessor, the binary value being representative of the presence or the absence of a stop code in the data.
Claim 3
Dependent Claim
111 words
A system according to claim 1, wherein the control circuit comprises an AND gate, receiving from the microprocessor or from the direct access circuit, signals having a logical level relating to input-output operations and controlling the writing or reading of the peripheral unit, one output of the AND gate being connected to a validation control input of the random access memory, and an OR gate receiving on one input the data address decoding signal from the memory while another input of the OR gate is connected to an output of the AND gate an output of the OR gate being connected to the writing control input of the random access memory.
Claim 4
Dependent Claim
142 words
A system according to claim 2, wherein the test circuit comprises an OR gate receiving the test control signal from the direct access circuit on one input while another input receives from the random access memory the binary value indicating that a stop code is present in the transferred data, and a R-S flip-flop, whereof one input is connected to an output of the OR gate of the test circuit and whereof a resetting input of the flip-flop is connected to the output of the OR gate of the control circuit, the output of said flip-flop being connected to a control input of the direct access circuit and to a control input of the microprocessor for supplying thereto a signal relating to the detection of an eventual stop code causing the interruption of the exchange and the interruption of the corresponding microprocessor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-10 | 1989-08-12 | 1990-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-10 | 1993-08-12 | 1994-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-10 | 1997-08-12 | 1998-02-11 | $7700.00 | Window Closed / Lapsed |