Abstract An electronic sample-and-hold circuit (10, 24) of the type which includes a correction network is designed to eliminate a primary signal feedback loop. A correction capacitor, (C C ), a coupling capacitor (C CC ), and a primary holding capacitor (C H ) are connected in series, respectively, between two ground points. The common node of the coupling capacitor and the holding capacitor is a held signal node (12). The common node of the coupling capacitor (C CC ) and the correction capacitor (C C ) is a correction voltage node (20). The circuit output is from the signal node (12) through a buffer (14) and a stage selecting switch (S F ). The output is fed back to an operational amplifier (18, 26) which has its output connected to the correction node (20) through a correction sampling switch (S C ). A switched (S A ) feedback loop connects the output of the amplifier 18 to the inverting input port. The primary signal input (IN) is to the signal node (12) through a primary sampling switch (S S ). The noninverting input (+) of the amplifier (26) is connected to the output of a buffer (22). The input of the buffer (22) receives the input signal through an input switch (S I ) and is also connected to an input capacitor (C I ), which has its other side grounded. Also disclosed is a circuit (24) in which the operational amplifier (26) is a less complex, inverting amplifier provided with a switched (S A ) local bypass loop.
A sample-and-hold circuit apparatus, comprising: first, second and third capacitors connected in series between two reference voltage points, the common node of the first and second capacitors forming a primary, signal node and the common node of the second and third capacitors forming a secondary, correction node; a feedback buffer having an input port and an output port, the input port being connected to the signal node; an amplifier having an inverting and a noninverting input and an output port, the output port being selectively connected to the correction node through a correction sampling switch; means for selectively connecting the output port of the amplifier to one of its input ports; means for selectively connecting an input signal to the signal node through a signal sampling switch, and means for selectively coupling the output port of the output buffer to the correction node through the amplifier.
Claim 2
Dependent Claim
146 words
A sample-and-hold circuit apparatus, comprising: first, second and third capacitors connected in series between two reference voltage points, the common node of the first and second capacitors forming a primary, signal node and the common node of the second and third capacitors forming a secondary, correction node; a feedback buffer having an input port and an output port, the input port being connected to the signal node; an amplifier having an inverting and a noninverting input and an output port, the output port being selectively connected to the correction node through a correction sampling switch; means for selectively connecting the output port of the amplifier to one of its input ports; means for selectively connecting an input signal to the signal node through a signal sampling switch, and means for selectively coupling the output port of the output buffer to the correction node through the amplifier.
Claim 3
Dependent Claim
87 words
The apparatus defined in claim 1 comprising: an input sampling switch having one side adapted to receive the input signal and having its other side connected to one side of an input holding capacitor, the other side of the input holding capacitor being connected to a reference potential, and an input buffer, the input port of the input buffer being connected to the one side of the input holding capacitor and the output of the input buffer being connected to the noninverting input port of the amplifier.
Claim 4
Dependent Claim
93 words
The apparatus defined in claim 1 comprising: an input buffer having its input adapted to receive an input signal and also connected to the signal node through the signal sampling switch; an input holding capacitor connected at one side to the inverting input port of the amplifier; means for selectively connecting the other side of the input holding capacitor alternately to the output port of the input buffer and to the output port of the feedback buffer, and means for selectively connecting the output port of the amplifier to its inverting input port.