US4569124A
Expired / Lapsed
US
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Method for forming thin conducting lines by ion implantation and preferential etching
Assignee: Raytheon Co
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Filing: 1984-05-22
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Granted: 1986-02-11
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Expires: 2004-05-22
Abstract
Abstract A thin conducting line such as a gate pattern is defined on a semiconductor chip (10) by applying a narrow ion beam, suitably a focused-ion-beam (16) having a submicrometer thickness from a source (18) onto a thin layer (14) of an inorganic material such as silicon or aluminum overlying a layer (12) of refractory metal on a substrate (11). The ion beam is translated to form a gate pattern at a dose between about 0.1 to 50x1015 cm-2 and an energy from about 1 to 1000 KeV. Ions are implanted into the silicon and aluminum layers and into the underlying portions of the refractory metal layer and to render the exposed portions of the layers preferentially resistant to wet-etchant. The portions of layers which are not exposed nor protected by layers which are exposed, are preferentially removed to form a gate. Conventional MOSFET or MESFET processing to implant ions to form source and drain regions may then be performed.
Inventors
- 👤 David B. Rensch
- 👤 John Y. Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:34
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/021; H10D30/0223; H10P; H10P32/00; H10P32/30; H10P32/302; H10P50/00; H10P50/20; H10P50/26; H10P50/264; H10P50/266; H10P50/267; H10P50/268; H10P50/60; H10P50/66; H10P50/663; H10P50/667; Y; Y10; Y10S; Y10S148/00; Y10S148/019; Y10S148/083; Y10S148/147; Y10S438/00; Y10S438/942
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
140 words
A method for forming conducting lines within microcircuits by ion implantation and preferential etching comprising the steps of: (a) providing a substrate; (b) applying a first layer of metal over a major surface of said substrate; (c) applying a second layer of inorganic material over said first layer of metal; (d) applying a narrow ion beam to said second and first layers so that said second layer is rendered preferentially etchant-resistant, a portion of said first layer is rendered preferentially etchant-resistant, and portions of said first layer underlying said etchant-resistant portion are protected during subsequent etching steps; and (e) selectively removing the areas of said second layer which are not rendered preferentially etchant-resistant, areas of said first layer which are not rendered preferentially etchant-resistant, and areas which are not protected by said etchant-resistant portions of said first and second layers.
Claim 2
Independent Claim
140 words
A method for forming conducting lines within microcircuits by ion implantation and preferential etching comprising the steps of: (a) providing a substrate; (b) applying a first layer of metal over a major surface of said substrate; (c) applying a second layer of inorganic material over said first layer of metal; (d) applying a narrow ion beam to said second and first layers so that said second layer is rendered preferentially etchant-resistant, a portion of said first layer is rendered preferentially etchant-resistant, and portions of said first layer underlying said etchant-resistant portion are protected during subsequent etching steps; and (e) selectively removing the areas of said second layer which are not rendered preferentially etchant-resistant, areas of said first layer which are not rendered preferentially etchant-resistant, and areas which are not protected by said etchant-resistant portions of said first and second layers.
Claim 3
Dependent Claim
18 words
The method of claim 1 wherein said substrate is selected from the group consisting of insulators and semiconductors.
Claim 4
Dependent Claim
23 words
The method of claim 2 wherein said substrate is a semiconductor and said ion of step (d) is a non-dopant in said semiconductor.
Claim 5
Dependent Claim
19 words
The method of claim 3 wherein said semiconductor is selected from the group consisting of silicon and III-V compounds.
Claim 6
Dependent Claim
28 words
The method of claim 4 wherein said substrate is silicon and includes a surface layer of silicon oxide between said silicon surface and said first layer of metal.
Claim 7
Dependent Claim
15 words
The method of claim 1 wherein said first layer of metal is a refractory metal.
Claim 8
Dependent Claim
22 words
The method of claim 1 wherein said second layer of inorganic material is selected from the group consisting of silicon and aluminum.
Claim 9
Dependent Claim
15 words
The method of claim 1 wherein said narrow ion beam is a focused ion beam.
Claim 10
Dependent Claim
31 words
The method of claim 8 further including the step of translating said ion beam relative to said second layer to form lines in the configuration of a gate for a FET.
Claim 11
Dependent Claim
35 words
The method of claim 9 wherein said substrate is a semiconductor and further including the step of implantating dopant ions to form source and drain regions in said substrate on both side of the gate.
Claim 12
Dependent Claim
30 words
The method of claim 10 wherein said ion beam has an energy from about 1 to 1,000 KeV and a dose of about 0.1 to 50×10 15 cm -2 .
Claim 13
Dependent Claim
17 words
The method of claim 8 wherein said ion beam has a width of less than 1 micrometer.
Claim 14
Dependent Claim
19 words
The method of claim 1 wherein said ion beam penetrates through said second layer and into said first layer.
Claim 15
Dependent Claim
56 words
The method of claim 13 wherein said second layer is less than about 150 Angstroms thick and said ion beam dosage is sufficiently low that said second layer becomes an integral part of the upper portion of said first layer due to mixing occurring during ion implantation so that the resultant combination becomes an etchant-resistant zone.
Claim 16
Dependent Claim
53 words
The method of claim 13 wherein said second layer is sufficiently thick that an ion-implanted second layer is obtained and said beam penetration beneath said second layer into said first layer results in interfacial mixing between said first and second layers wilth simultaneous ion implantation, wherein said interfacial area becomes an etchant-resistant zone.
Claim 17
Dependent Claim
40 words
The method of claim 15 wherein said second layer is silicon and said beam penetration into said first layer results in the interfacial area between said first layer and said second layer becoming a zone of etchant-resistant ion-implanted metal silicide.
Claim 18
Dependent Claim
71 words
A wafer for use in forming a FET device comprising: a semiconductor substrate; a first layer of refractory metal formed on said substrate; and a second layer of inorganic material formed on said first layer, wherein portions of said second layer are rendered preferentially resistant to etchant when said portions are implanted with ions having an energy above 1 KeV and a dose of 0.1 to 15×10 15 cm -2 .
Claim 19
Dependent Claim
71 words
A wafer for use in forming a FET device comprising: a semiconductor substrate; a first layer of refractory metal formed on said substrate; and a second layer of inorganic material formed on said first layer, wherein portions of said second layer are rendered preferentially resistant to etchant when said portions are implanted with ions having an energy above 1 KeV and a dose of 0.1 to 15×10 15 cm -2 .
Claim 20
Dependent Claim
20 words
The wafer according to claim 17 wherein said second layer is selected from the group consisting of aluminum and silicon.
Claim 21
Dependent Claim
21 words
The wafer according to claim 17 further including a layer of oxide between the substrate and the first layer of metal.
Claim 22
Dependent Claim
38 words
The wafer according to claim 17 wherein said portions of said first layer underlying the ion-implanted portions of said second layer contain an etchant-resistant pattern, such pattern comprising interfacially mixed said first and second layers and implanted ions.
Claim 23
Dependent Claim
19 words
The wafer according to claim 20 in which said pattern contains lines having a length less than 1 micrometer.
Claim 24
Dependent Claim
30 words
The wafer according to claim 20 in which all but said etchant-resistant portions of both layers and portions of said first layer protected by said etchant-resistant portions have been removed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-10 | 1989-08-12 | 1990-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-10 | 1993-08-12 | 1994-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-10 | 1997-08-12 | 1998-02-11 | $7700.00 | Window Closed / Lapsed |