US4569119A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Manufacturing method of Schottky gate FET
Assignee: Toshiba Corp
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Filing: 1984-06-07
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Granted: 1986-02-11
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Expires: 2004-06-07
Abstract
Abstract An etched SiO 2 film component serving as a mask at the time of formation of source and drain electrodes in a surface layer of a GaAs substrate by means of ion implantation is side-etched before a gate electrode is formed. An SiO 2 film component has a narrowed width smaller than a distance between the source and drain electrodes while the SiO 2 film component supports a metal mask patterned film at its top surface. The SiO 2 film component is replaced with a metal layer serving as a gate of a self-aligned Schottky gate FET. According to this method, a metal with high heat resistance need not be used as a metal material of the gate layer.
Inventors
- 👤 Toshiyuki Terada
- 👤 Nobuyuki Toyoda
- 👤 Akimichi Hojo
- 👤 Kiyoho Kamei
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 00:24
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0614; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D30/6738; H10D30/674; H10D30/675; H10D30/80; H10D30/87; H10D64/00; H10D64/60; H10D64/64; H10D62/00; H10D62/80; H10D62/85
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
192 words
A method of manufacturing a Schottky gate type field effect transistor having gate, source and drain electrodes, said method comprising the steps of: (a) etching an insulating layer on a compound semiconductor substrate to obtain an insulating layer component having a first width so as to define a prospective gate electrode formation region; (b) implanting ions into said substrate to form in said compound semiconductor substrate first and second semiconductor regions corresponding to the source and drain electrodes of the transistor, said first and second semiconductor regions being self-aligned with said insulating layer component; (c) side-etching said insulating layer component so that said insulating layer component has a second width smaller than the first width; (d) annealing said compound semiconductor substrate; and (e) replacing said insulating layer component having the second width with a metal layer corresponding to the gate electrode, whereby a width of the gate electrode thus obtained is smaller than a distance between the source and drain electrodes so as to decrease capacitances between the gate electrode and the source electrode and between the gate electrode and the drain electrode; said steps (a)-(e) being performed in the order listed.
Claim 2
Independent Claim
192 words
A method of manufacturing a Schottky gate type field effect transistor having gate, source and drain electrodes, said method comprising the steps of: (a) etching an insulating layer on a compound semiconductor substrate to obtain an insulating layer component having a first width so as to define a prospective gate electrode formation region; (b) implanting ions into said substrate to form in said compound semiconductor substrate first and second semiconductor regions corresponding to the source and drain electrodes of the transistor, said first and second semiconductor regions being self-aligned with said insulating layer component; (c) side-etching said insulating layer component so that said insulating layer component has a second width smaller than the first width; (d) annealing said compound semiconductor substrate; and (e) replacing said insulating layer component having the second width with a metal layer corresponding to the gate electrode, whereby a width of the gate electrode thus obtained is smaller than a distance between the source and drain electrodes so as to decrease capacitances between the gate electrode and the source electrode and between the gate electrode and the drain electrode; said steps (a)-(e) being performed in the order listed.
Claim 3
Dependent Claim
115 words
The method according to claim 1, wherein the step of replacing said insulating layer component with the gate electrode comprises substeps of: forming an organic layer on a structure wherein said insulating layer component having the second width is formed on said compound semiconductor substrate in such a manner that a top surface of said insulating layer component is exposed; removing said insulating layer component, whereby said organic layer has an opening which has substantially the same size as the second width of said insulating layer component, said compound semiconductor substrate being partially exposed through said opening; and forming the metal layer on an exposed surface portion of said compound semiconductor substrate through said opening.
Claim 4
Dependent Claim
41 words
The method according to claim 2, wherein said organic layer having said opening is removed from said compound semiconductor substrate according to a lift-off process, after said metal layer is formed on said exposed surface portion of said compound semiconductor substrate.
Claim 5
Dependent Claim
37 words
The method according to claim 3, wherein said insulating layer component having the first width is etched by chemical dry etching at both side wall surfaces thereof by a given distance only substantially along a lateral direction.
Claim 6
Dependent Claim
14 words
The method according to claim 3, wherein said organic layer comprises a photoresist material.
Claim 7
Dependent Claim
69 words
The method according to claim 4, further comprising the step of forming a mask layer defining the prospective gate electrode formation region of said compound semiconductor substrate, said mask layer being formed on said insulating layer formed on said compound semiconductor substrate, whereby a portion of said insulating layer which is present under said mask layer is left as said insulating layer component obtained by etching said insulating layer.
Claim 8
Dependent Claim
33 words
The method according to claim 6, wherein said mask layer is left on said insulating layer component through ion-implanting for forming the source and drain electrodes and side-etching of said insulating layer component.
Claim 9
Dependent Claim
22 words
The method according to claim 7, wherein said mask layer is removed from said insulating layer component before said substrate is annealed.
Claim 10
Dependent Claim
14 words
The method according to claim 8, wherein said mask layer comprises a metal material.
Claim 11
Dependent Claim
14 words
The method according to claim 8, wherein said mask layer comprises a photoresist material.
Claim 12
Dependent Claim
44 words
The method according to claim 8, further comprising the step of forming in said compound semiconductor substrate an electrically active layer on which said insulating layer component with said mask layer is positioned, before said insulating layer is formed on said compound semiconductor substrate.
Claim 13
Dependent Claim
106 words
The method according to claim 8, wherein the step of forming on said compound semiconductor substrate said organic layer such that said top surface of said insulating layer component is exposed, comprises the substeps of: applying an organic material on an entire surface of said compound semiconductor substrate having the source and drain electrodes and said insulating layer component of the second width, said organic material including a photoresist material; and etching a surface portion of a photoresist layer of the organic material by anisotropic etching, thereby decreasing a thickness of said photoresist layer so as to expose said top surface of said insulating layer component.
Claim 14
Dependent Claim
105 words
The method according to claim 8, wherein the step of forming on said compound semiconductor substrate said photoresist layer such that said top surface of said insulating layer component is exposed, comprises the substeps of: applying an organic material on an entire surface of said compound semiconductor substrate having the source and drain electrodes and said insulating layer component of the second width, said organic material including a photoresist material; and partially recessing a portion of a photoresist layer of the organic material and performing anisotropic etching to expose the top surface of said insulating layer component through a bottom surface of a recessed portion.
Claim 15
Dependent Claim
14 words
The method according to claim 5, wherein said compound semiconductor substrate comprises gallium arsenide.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1989-02-10 | 1989-08-12 | 1990-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-10 | 1993-08-12 | 1994-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-10 | 1997-08-12 | 1998-02-11 | $7700.00 | Window Closed / Lapsed |