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US4568841A
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Flexible timing circuit
Assignee: Enterasys Networks Inc
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Filing: 1983-03-28
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Granted: 1986-02-04
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Expires: 2003-03-28
Abstract
Abstract The present invention includes a counter device which counts pulses from a pulse source and provides the basis for a control gate signal. Logic circuitry is connected to the counter device and through said logic circuitry there are provided the leading edge, the interim voltage level signal, and the trailing edge of said control gate signal. The counter device is connected from at least two latter stages to said logic circuitry to provide two possible trailing edges, which in turn selectively define two different length gate signals. Said logic circuitry is further connected to address signal circuitry and in response to a first address provides a control gate signal of a first length and in response to a second address provides a control gate signal of a second length.
Inventors
- 👤 Steven C. Mayhew
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:58
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/84
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
202 words
A timing circuit to be used with a data communications system to alter the time period of at least one control gate signal from a time period of X to a time period of X+N comprising in combination: repetitive signal source means; start and stop signal generating means for providing a start signal as well as first and second stop signals, each of said stop signals being respectively generated at a different length of time from said start signal, said start and stop signal generating means connected to said repetitive signal source means for operating in response to receiving repetitive signals; address signal generating means for providing at least first and second address signals; logic circuitry connected to said start and stop signal generating means and to said address signal generating means, for receiving a start signal and in response, to said start signal, providing the leading edge of a control gate signal and further for receiving said first stop signal and said first address signal for providing a first trailing edge signal for said control gate signal and alternatively for receiving said second stop signal and said second address signal for providing a second trailing-edge signal for said control gate signal.
Claim 2
Dependent Claim
202 words
A timing circuit to be used with a data communications system to alter the time period of at least one control gate signal from a time period of X to a time period of X+N comprising in combination: repetitive signal source means; start and stop signal generating means for providing a start signal as well as first and second stop signals, each of said stop signals being respectively generated at a different length of time from said start signal, said start and stop signal generating means connected to said repetitive signal source means for operating in response to receiving repetitive signals; address signal generating means for providing at least first and second address signals; logic circuitry connected to said start and stop signal generating means and to said address signal generating means, for receiving a start signal and in response, to said start signal, providing the leading edge of a control gate signal and further for receiving said first stop signal and said first address signal for providing a first trailing edge signal for said control gate signal and alternatively for receiving said second stop signal and said second address signal for providing a second trailing-edge signal for said control gate signal.
Claim 3
Dependent Claim
24 words
A timing circuit according to claim 1 wherein said start and stop signal generating means includes a counter device with a plurality of stages.
Claim 4
Dependent Claim
55 words
A timing circuit according to claim 2 wherein said counter has a first stage with an output means for providing said start signal and has an X th stage with an output means for providing said first stop signal and has an (X+N) th stage with an output means for providing said second stop signal.
Claim 5
Dependent Claim
73 words
A timing circuit according to claim 3 wherein said logic circuit includes a two state circuit having first and second output means whereby in response to said start signal said two state circuit provides said leading edge of said control gate signal and in response respectively to said first stop signal and said second stop signal said two state circuit provides respectively said first and second trailing edges of said control gate signals.
Claim 6
Dependent Claim
71 words
A timing circuit according to claim 1 wherein said logic circuitry includes at least first and second gate circuitry and wherein said first gate circuitry is connected to receive said first stop signal and said first address signal to provide a first trailing edge signal and wherein said second gate circuitry is connected to receive said second stop signal and said second address signal to provide a second trailing edge signal.
Claim 7
Dependent Claim
16 words
A timing circuit according to claim 4 wherein said two state circuit is a bistable multivibrator.
Claim 8
Dependent Claim
65 words
A timing circuit according to claim 5 wherein said first and second gate circuitry are connected to further logic circuits and wherein there is included reset circuitry connected between said further logic circuits and said start and stop signal generating means to reset said start and stop signal generating means in response to an output signal from any of said first and second gate circuitry.
Claim 9
Dependent Claim
59 words
A timing circuit according to claim 7 wherein said further logic circuits perform an OR function and wherein there is further included in said logic circuitry a two state circuit which is connected in one state to receive the output of said further logic circuits to provide, alternatively, said first and second trailing edges of said control gate signal.
Claim 10
Dependent Claim
33 words
A timing circuit according to claim 8 wherein, in the other state, said two state circuit is connected to receive said start signal for providing the trailing edge of a control gate signal.
Claim 11
Dependent Claim
20 words
A timing circuit according to claim 9 wherein said start and stop signal generating means comprises a multi stage counter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-03 | 1989-08-05 | 1990-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-03 | 1993-08-05 | 1994-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-03 | 1997-08-05 | 1998-02-04 | $7700.00 | Window Closed / Lapsed |