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US4566119A
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Equalizer networks and methods of developing scaling coefficients therefor
Assignee: BENN BRIAN
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Filing: 1983-10-12
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Granted: 1986-01-21
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Expires: 2003-10-12
Abstract
Abstract An adjustable equalizer network comprises a series chain of N all pass amplifier stages driving M minimum phase shift transversal filters connected to a final summing circuit that includes means to adjust each filter output to obtain a ripple free predetermined frequency response over a given frequency range. Each filter includes N+1 scaling circuits connected to an intermediate summing circuit; the scaling circuits have scaling coefficients, of magnitude and sign determined by Fourier analysis and an appropriate truncation function, such that the filter has a pass band representative of one of M contiguous bands conjointly encompassing the frequency range. The adjustable equalizer, once adjusted for a desired frequency response, may be supplied with a DC reference input and used to determine the contribution (magnitude and sign) to the frequency response from each tap on the all pass chain, thus developing a set of N+1 scaling coefficients for a simplified equalizer network, comprising the all pass chain with just one set of N+1 scaling circuits, that duplicates the response characteristic of the more complex adjustable equalizer. Some embodiments incorporate digital programming and control of the frequency response characteristic.
Inventors
- 👤 Richard W. Peters
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:21
CPC Classifications
H; H03; H03G; H03G5/00; H03G5/02; H03G5/025
Claims Analysis
Total Claims: 75
Claim 1
Independent Claim
167 words
A minimum-phase equalizer network adapted to develop an equalized output signal having a predetermined frequency response characteristic, with minimum ripple, over a preselected frequency range, comprising: a series chain of N all pass delay stages, the chain having an initial tap connected to the input to the first stage in the chain and N additional taps each connected to the output of a succeeding stage in the chain; M minimum-phase transversal filters, all connected to and each including the entire series chain of all pass delay stages as a part thereof, each filter developing an intermediate signal within a pass band representative of one of a contiguous series of M nominal frequency bands extending across the frequency range; final summing circuit means for additively combining the intermediate signals in predetermined amplitude relation to each other to develop the equalized output signal; and adjusting means for adjusting the amplitude of each intermediate signal, independently of the others, to adjust the overall frequency response characteristic of the equalizer network.
Claim 2
Dependent Claim
167 words
A minimum-phase equalizer network adapted to develop an equalized output signal having a predetermined frequency response characteristic, with minimum ripple, over a preselected frequency range, comprising: a series chain of N all pass delay stages, the chain having an initial tap connected to the input to the first stage in the chain and N additional taps each connected to the output of a succeeding stage in the chain; M minimum-phase transversal filters, all connected to and each including the entire series chain of all pass delay stages as a part thereof, each filter developing an intermediate signal within a pass band representative of one of a contiguous series of M nominal frequency bands extending across the frequency range; final summing circuit means for additively combining the intermediate signals in predetermined amplitude relation to each other to develop the equalized output signal; and adjusting means for adjusting the amplitude of each intermediate signal, independently of the others, to adjust the overall frequency response characteristic of the equalizer network.
Claim 3
Dependent Claim
162 words
An equalizer network according to claim 1 in which each filter circuit comprises: an initial scaling circuit connected to the initial top of the chain and having a scaling coefficient a 0 determined approximately by ##EQU14## N additional scaling circuits, each connected to one of the additional taps, each additional scaling circuit having a scaling coefficient a n determined approximately by ##EQU15## in which: n is the number of any given all pass stage in the chain, θ m+1 and θ m are the phase shifts for one of the all pass stages at the upper and lower frequencies, respectively, of the nominal frequency band for each of the M filters, and W(n) is a truncating function to smooth the overall frequency responses of the filters; and intermediate summing circuit means for additively combining the outputs of all of the scaling circuits, in the polarities determined by their respective scaling coefficients, to develop an intermediate signal as an output from the filter.
Claim 4
Dependent Claim
10 words
An equalizer network according to claim 2 in which ##EQU16##
Claim 5
Dependent Claim
10 words
An equalizer network according to claim 3 in which M≈N/2.
Claim 6
Dependent Claim
71 words
An equalizer network according to claim 2 in which each intermediate summing circuit means comprises: a non-inverting bus to which all scaling circuits having positive scaling coefficients are connected; an inverting bus to which all scaling circuits having negative scaling coefficients are connected; and an adding amplifier for adding signals from the the two buses together, with the signals from one bus inverted relative to the signals from the other bus.
Claim 7
Dependent Claim
14 words
An equalizer network according to claim 5 in which ##EQU17## and in which M≈N/2.
Claim 8
Dependent Claim
59 words
An equalizer network according to claim 6 in which N is determined in accordance with the relationship ##EQU18## in which: ##EQU19## f L is the lower limit of the frequency range, f H is the upper limit of the frequency range, f H f L =f 0 2 , and RC is the time constant of each delay stage.
Claim 9
Dependent Claim
59 words
An equalizer network according to claim 1 in which N is determined in accordance with the relationship ##EQU20## in which: ##EQU21## f L is the lower limit of the frequency range, f H is the lower limit of the frequency range, f H f L =f 0 2 , and RC is the time constant of each delay stage.
Claim 10
Dependent Claim
162 words
An equalizer network according to claim 8 in which each filter circuit comprises: an initial scaling circuit connected to the initial tap of the chain and having a scaling coefficient a 0 determined approximately by ##EQU22## N additional scaling circuits, each connected to one of the additional taps, each additional scaling circuit having a scaling coefficient a n determined approximately by ##EQU23## in which: n is the number of any given all pass stage in the chain, θ m+1 and θ m are the phase shifts for one of the all pass stages at the upper and lower frequencies, respectively, of the nominal frequency band for each of the M filters, and W(n) is a truncating function to smooth the overall frequency responses of the filters; and intermediate summing circuit means for additively combining the outputs of all of the scaling circuits, in the polarities determined by their respective scaling coefficients, to develop an intermediate signal as an output from the filter.
Claim 11
Dependent Claim
10 words
An equalizer network according to claim 9 in which ##EQU24##
Claim 12
Dependent Claim
10 words
An equalizer network according to claim 10 in which M≈N/2.
Claim 13
Dependent Claim
49 words
An equalizer network according to claim 1 and further comprising: switching means including a series of N+1 switches, each interposed between one tap of the chain and all of the filters, to allow measurement of the total contribution of each tap to the overall frequency response of the network.
Claim 14
Dependent Claim
161 words
An equalizer network according to claim 12 in which each filter comprises: an initial scaling circuit connected to the initial tap of the chain and having a scaling coefficient a 0 determined approximately by ##EQU25## N additional scaling circuits, each connected to one of the additional taps, each additional scaling circuit having a scaling coefficient a n determined approximately by ##EQU26## in which: n is the number of any given all pass stage in the chain, θ m+1 and θ m are the phase shifts for one of the all pass stages at the upper and lower frequencies, respectively, of the nominal frequency band for each of the M filters, and W(n) is a truncating function to smooth the overall frequency response of the filter; and intermediate summing circuit means for additively combining the outputs of all of the scaling circuits, in the polarities determined by their respective scaling coefficients, to develop an intermediate signal as an output from the filter.
Claim 15
Dependent Claim
13 words
An equalizer network according to claim 13 in which ##EQU27## in which M≈N/2.
Claim 16
Dependent Claim
59 words
An equalizer network according to claim 14 in which N is determined in accordance with the relationship ##EQU28## in which: ##EQU29## f L is the lower limit of the frequency range, f H is the upper limit of the frequency range, f H f L =f 0 2 , and RC is the time constant of each delay stage.
Claim 17
Dependent Claim
17 words
An equalizer network according to claim 12 in which each switch is a signal-actuated electronic switching device.
Claim 18
Dependent Claim
114 words
An equalizer network according to claim 16, adapted to generation of a series of equalization scaling coefficient control signals, and further comprising: clock signal generator means for generating a clock signal; counter means, actuated by the clock signal, for generating a predetermined sequence of N+1 digital address signals and a corresponding sequence of write command signals; analog/digital convertor means, having inputs comprising the clock signal, the write command signals, and a DC output signal from the summing circuit means, for generating a corresponding sequence of digital scaling control signals; and decoder means, actuated by the address signals and having individual outputs to the switching devices, for closing the switching devices in said predetermined sequence.
Claim 19
Dependent Claim
79 words
An equalizer network according to claim 12, adapted to generation of a program of scaling resistance values for use in another equalizer, and further comprising: analog/digital convertor means, connected to the output of the final summing circuit means, for generating a sequence of N+1 digital signals representative of scaling resistance values corresponding to the DC outputs of the final summing circuit produced by applying a reference DC input to the equalizer and closing the switches one at a time.
Claim 20
Dependent Claim
162 words
An equalizer network according to claim 18 in which each filter circuit comprises: an initial scaling circuit connected to the initial tap of the chain and having a scaling coefficient a 0 determined approximately by ##EQU30## N additional scaling circuits, each connected to one of the additional taps, each additional scaling circuit having a scaling coefficient a n determined approximately by ##EQU31## in which: n is the number of any given all pass stage in the chain, θ m+1 and θ m are the phase shifts for one of the all pass stages at the upper and lower frequencies, respectively, of the nominal frequency band for each of the M filters, and W(n) is a truncating function to smooth the overall frequency responses of the filters; and intermediate summing circuit means for additively combining the outputs of all of the scaling circuits, in the polarities determined by their respective scaling coefficients, to develop an intermediate signal as an output from the filter.
Claim 21
Dependent Claim
14 words
An equalizer network according to claim 19 in which ##EQU32## and in which M≈N/2.
Claim 22
Dependent Claim
59 words
An equalizer network according to claim 20 in which N is determined in accordance with the relationship ##EQU33## in which: ##EQU34## f L is the lower limit of the frequency range, f H is the upper limit of the frequency range, f H f L =f 0 2 , and RC is the time constant of each delay stage.
Claim 23
Dependent Claim
22 words
An equalizer network according to claim 18, and further comprising a digital readout indicator connected to the output of the analog/digital convertor.
Claim 24
Dependent Claim
17 words
An equalizer network according to claim 22 in which each switch is a signal-actuated electronic switching device.
Claim 25
Dependent Claim
195 words
A minimum-phase equalizer network adapted to develop an equalized output output signal having a predetermined frequency response characteristic with minimum ripple, over a preselected frequency range, comprising: a series chain of N all pass delay stages, the chain having an initial tap connected to the input to the first stage in the chain and N additional taps each connected to the output of a succeeding stage in the chain; N+1 scaling circuits, each connected to one of the taps, each scaling circuit having a scaling coefficient with a magnitude and polarity representative of the algebraic sum of the scaling coefficients, for the tap to which the scaling circuit is connected, that would be incorporated in a group of M smoothly truncated minimum-phase transversal filters covering contiguous frequency bands encompassing the preselected frequency range and driven by all stages in a corresponding chain of N all pass delay stages, which M filters would conjointly afford the predetermined frequency response characteristic over the preselected frequency range; and summing circuit means for additively combining the outputs of all of the scaling circuits, in the polarity relationships determined by their respective scaling coefficients, to develop the equalized output signal.
Claim 26
Dependent Claim
195 words
A minimum-phase equalizer network adapted to develop an equalized output output signal having a predetermined frequency response characteristic with minimum ripple, over a preselected frequency range, comprising: a series chain of N all pass delay stages, the chain having an initial tap connected to the input to the first stage in the chain and N additional taps each connected to the output of a succeeding stage in the chain; N+1 scaling circuits, each connected to one of the taps, each scaling circuit having a scaling coefficient with a magnitude and polarity representative of the algebraic sum of the scaling coefficients, for the tap to which the scaling circuit is connected, that would be incorporated in a group of M smoothly truncated minimum-phase transversal filters covering contiguous frequency bands encompassing the preselected frequency range and driven by all stages in a corresponding chain of N all pass delay stages, which M filters would conjointly afford the predetermined frequency response characteristic over the preselected frequency range; and summing circuit means for additively combining the outputs of all of the scaling circuits, in the polarity relationships determined by their respective scaling coefficients, to develop the equalized output signal.
Claim 27
Dependent Claim
58 words
An equalizer network according to claim 24 in which N is determined in accordance with the relationship ##EQU35## in which: ##EQU36## f L is the lower limit of the frequency range, f H is the upper limit of the frequency range, f H f L =f 0 2 and RC is the time constant for each delay stage.
Claim 28
Dependent Claim
10 words
An equalizer network according to claim 25 in which M≈N/2.
Claim 29
Dependent Claim
69 words
An equalizer network according to claim 26 in which the summing circuit means comprises: a non-inverting bus to which all scaling circuits having positive scaling coefficients are connected; an inverting bus to which all scaling circuits having negative scaling coefficients are connected; and an adding amplifier for adding signals from the two buses together, with the signals from one bus inverted relative to the signals from the other bus.
Claim 30
Dependent Claim
69 words
An equalizer network according to claim 24 in which the summing circuit means comprises: a non-inverting bus to which all scaling circuits having positive scaling coefficients are connected; an inverting bus to which all scaling circuits having negative scaling coefficients are connected; and an adding amplifier for adding signals from the two buses together, with the signals from one bus inverted relative to the signals from the other bus.
Claim 31
Dependent Claim
172 words
An equalizer network according to claim 24 in which each of the M filters comprises: an initial filter scaling circuit connected to the initial tap of the chain and having a scaling coefficient a O determined approximately by ##EQU37## N additional filter scaling circuits, each connected to one of the additional taps, each additional scaling circuit having a scaling coefficient a n determined approximately by ##EQU38## in which: n is the number of any given all pass stage in the chain, θ m+1 and θ m are the phase shifts for one of the all the pass stages at the upper and lower frequencies, respectively, of the nominal frequency band for each of the M filters, and W(n) is a truncating function to smooth the overall frequency responses of the filters; summing circuit means for additively combining the outputs of all of the filter scaling circuits, in the polarities determined by their respective scaling coefficients, to develop a filter output signal; and means to adjust the amplitude of the filter output signal.
Claim 32
Dependent Claim
10 words
An equalizer network according to claim 29 in which ##EQU39##
Claim 33
Dependent Claim
10 words
An equalizer network according to claim 30 in which M≈N/2.
Claim 34
Dependent Claim
58 words
An equalizer network according to claim 29 in which N is determined in accordance with the relationship ##EQU40## in which: ##EQU41## f L is the lower limit of the frequency range, f H is the upper limit of the frequency range, f H f L =f 0 2 and RC is the time constant for each delay stage.
Claim 35
Dependent Claim
72 words
An equalizer network according to claim 29 in which the summing circuit means for each filter comprises: a non-inverting bus to which all scaling circuits having positive scaling coefficients are connected; an inverting bus to which all scaling circuits having negative scaling coefficients are connected; and an adding amplifier for adding signals from the two buses together, with the signals from one bus inverted relative to the signals from the other bus.
Claim 36
Dependent Claim
41 words
An equalizer network according to claim 24 in which each scaling circuit comprises: a parallel connected plurality of scaling resistances; and scaling resistance switching means, comprising a corresponding plurality of scaling resistance switches each connected to series with the scaling resistances.
Claim 37
Dependent Claim
94 words
An equalizer network according to claim 34 in which the summing circuit means comprises: a non-inverting bus to which all scaling circuits having positive scaling coefficients are connected; an inverting bus to which all scaling circuits having negative scaling coefficients are connected; and an adding amplifier for adding signals from the two buses together, with the signals from one bus inverted relative to the signals from the other bus; and in which each scaling circuit further comprises polarity switching means to connect the scaling circuit to either the inverting bus or the non-inverting bus.
Claim 38
Dependent Claim
35 words
An equalizer network according to claim 34 in which the scaling resistance in each scaling circuit comprise a binary series, in magnitude, each successive resistance twice the magnitude of the prior resistance in the series.
Claim 39
Dependent Claim
94 words
An equalizer network according to claim 36 in which the summing circuit means comprises: a non-inverting bus to which all scaling circuits having positive scaling coefficients are connected; an inverting bus to which all scaling circuits having negative scaling coefficients are connected; and an adding amplifier for adding signals from the two buses together, with the signals from one bus inverted relative to the signals from the other bus; and in which each scaling circuit further comprises polarity switching means to connect the scaling circuit to either the inverting bus or the non-inverting bus.
Claim 40
Dependent Claim
99 words
An equalizer network according to claim 24 in which each scaling circuit comprises multiplying circuit means for multiplying an input signal, from the chain output tap associated therewith, by a scaling coefficient determined by a scaling control signal input to the multiplying circuit means, and in which the equalizer network further comprises scaling control signal generator means, connected to all of the multiplying circuit means, for supplying a series of scaling control signals to the multiplying circuit means, each scaling control signal representative of the scaling coefficient for the scaling circuit in which the multiplying circuit means is incorporated.
Claim 41
Dependent Claim
49 words
An equalizer network according to claim 38 in which each multiplying circuit means comprises a multiplying digital to analog converter, and in which each scaling control signal from the scaling signal generator means is a digital signal indicative of both amplitude and polarity of the scaling coefficient represented thereby.
Claim 42
Dependent Claim
58 words
An equalizer network according to claim 39 in which N is determined in accordance with the relationship ##EQU42## in which: ##EQU43## f L is the lower limit of the frequency range, f H is the upper limit of the frequency range, f H f 1 =f 0 2 and RC is the time constant for each delay stage.
Claim 43
Dependent Claim
26 words
An equalizer network according to claim 40 in which the scaling coefficients for the equalizer network are based on a group of M filters, and M≈N/2.
Claim 44
Dependent Claim
224 words
An equalizer network according to claim 38 in which the scaling control signal generator means comprises: a series chain of N all pass delay stages, the chain having an initial tap connected to the input to the first stage in the chain and N additional taps each connected to the output of a succeeding stage in the chain; M minimum-phase transversal filters, all of the filters being connected to and each filter including the entire series chain of all pass delay stages of the scaling control signal generator, each filter developing an intermediate signal within a pass band representative of one of a contiguous series of M nominal frequency bands extending across the frequency range; N+1 signal-actuated electronic switching devices, each interposed between one tap of the scaling control signal generator chain of all pass delay stages and all of the filters of that signal generator; summing circuit means for additively combining the intermediate signals from the scaling control signal generator filters; and analog/digital convertor means, connected to the output of the summing circuit means of the scaling control signal generator, for generating a sequence of N+1 digital scaling control signals representative of scaling coefficient values corresponding to the DC outputs of the summing circuit produced by applying a reference DC input to the equalizer and closing the electronic switching individually in predetermined sequence.
Claim 45
Dependent Claim
113 words
An equalizer network according to claim 42 in which the analog/digital convertor means of the scaling control signal generator comprises: clock signal generator means for generating a clock signal; counter means, actuated by the clock signal, for generating a predetermined sequence of N+1 digital address signals and a corresponding sequence of write command signals; an analog/digital convertor circuit, having inputs comprising the clock signal, the write command signals, and the DC output signals from the summing circuit means, for generating a corresponding sequence of digital scaling control signals; and decoder means, actuated by the address signals and having individual outputs to the switching devices, for closing the switching devices in said predetermined sequence.
Claim 46
Dependent Claim
49 words
An equalizer network according to claim 43 in which each multiplying circuit means comprises a multiplying digital to analog converter, and in which each scaling control signal from the scaling signal generator means is a digital signal indicative of both amplitude and polarity of the scaling coefficient represented thereby.
Claim 47
Dependent Claim
58 words
An equalizer network according to claim 44 in which N is determined in accordance with the relationship ##EQU44## in which: ##EQU45## f L is the lower limit of the frequency range, f H is the upper limit of the frequency range, f H f 1 =f 0 2 and RC is the time constant for each delay stage.
Claim 48
Dependent Claim
26 words
An equalizer network according to claim 45 in which the sealing coefficients for the equalizer network are based on a group of M filters, and M≈N/2.
Claim 49
Dependent Claim
186 words
An equalizer network according to claim 38 in which the scaling signal control generator means comprises: reference signal generator means for generating a series of M DC reference signals H 1 through H M conjointly representative of the frequency response characteristic of the equalizer network in accordance with the relationship ##EQU46## multiplier means for multiplying the reference signals by a sequence of function data signals representative of the function ##EQU47## in which n is the number of one stage in the all pass chain, θ is the phase shift of any signal of frequency f within the operational range of any delay stage in the chain, and θ m+1 and θ m are the phase shifts for one of the all pass filters at the upper and lower frequencies, respectively, of the nominal pass band for each of the M filters, to develop a series of sequences of intermediate scaling coefficient signals; and accumulator means for adding each sequence of intermediate scaling coefficient signals to generate a series of scaling control signals each representative of the scaling coefficient for one scaling circuit in the equalizer network.
Claim 50
Dependent Claim
53 words
An equalizer network according to claim 47 in which: the multiplying circuit means in each scaling circuit comprises a multiplying digital to analog convertor having a digital multiplier memory; and the function data signals and scaling control signals are digital signals indicative of both amplitude and polarity of the scaling coefficients represented thereby.
Claim 51
Dependent Claim
90 words
An equalizer network according to claim 48 in which the scaling signal control generator means further comprises: digital memory means for storing the sequence of function data signals, the digital memory means having an output connected to the multiplier means; multiplexer means, interposed between the reference signal generator means and the multiplier means, for supplying the reference signals to the multiplier means in predetermined time sequence; and clock means connected to and actuating the multiplexer means, the digital memory means, and the accumulator means in timed coordination with each other.
Claim 52
Dependent Claim
145 words
An equalizer network according to claim 49 and further comprising: reset counter means, in the clock means, for generating a reset signal, supplied to the accumulator means to terminate accumulation of each scaling control signal; write bus means for applying the reset signal to the multiplying convertors in the scaling circuits as a write command signal for recording the scaling control signals in the multiplier memories thereof; address counter means, in the clock means, for generating a repeating sequence of N unique address signals, one for each scaling circuit, with the change to the next address signal occurring in one-for-one synchronism with the reset signal; and address bus and decoder means for applying the address signals to the multiplying convertors in the scaling circuits to limit recording of each scaling control signal to the multiplier memory in the multiplying convertor of just one scaling circuit.
Claim 53
Dependent Claim
58 words
An equalizer network according to claim 50 in which N is determined in accordance with the relationship ##EQU48## in which: ##EQU49## f L is the lower limit of the frequency range, f H is the upper limit of the freqency range, f H f 1 =f 0 2 and RC is the time constant for each delay stage.
Claim 54
Dependent Claim
26 words
An equalizer network according to claim 51 in which the scaling coefficients for the equalizer network are based on a group of M filters, and M≈N/2.
Claim 55
Dependent Claim
309 words
A scaling control signal generator for generating a series of scaling control signals for a simplified equalizer network comprising a series chain of N all pass delay stages having an initial output tap connected to the input to the first stage in the chain and N additional output taps each connected to the output of a succeeding stage in the chain, N+1 scaling circuits each connected to one of the output taps, each scaling circuit including a multiplying digital to analog convertor for multiplying an input signal from the associated chain output tap by a digital scaling control signal indicative of a scaling coefficient, and summing circuit means for additively combining the outputs of all of the scaling circuits in the polarity relationships determined by their respective scaling coefficients, the scaling control signal generator comprising: reference signal generator means for generating a series of M DC reference signals H 1 through H M conjointly representative of the frequency response characteristic of the equalizer network in accordance with the relationship ##EQU50## multiplier means for multiplying the reference signals by a sequence of digital function data signals representative of the Fourier function series ##EQU51## in which n is the number of one stage in the all pass chain, θ is the phase shift of any signal of frequency f within the operational range of any delay stage in the chain, and θ m+1 and θ m are the phase shifts for one of the all pass delay stages at the upper and lower frequencies, respectively, of the nominal pass band for each of the delay stages to develop a series of sequences of intermediate scaling coefficient signals; and accumulator means for adding each sequence of intermediate scaling coefficient signals to generate a series of scaling control signals each representative of the scaling coefficient for one scaling circuit in the equalizer network.
Claim 56
Dependent Claim
309 words
A scaling control signal generator for generating a series of scaling control signals for a simplified equalizer network comprising a series chain of N all pass delay stages having an initial output tap connected to the input to the first stage in the chain and N additional output taps each connected to the output of a succeeding stage in the chain, N+1 scaling circuits each connected to one of the output taps, each scaling circuit including a multiplying digital to analog convertor for multiplying an input signal from the associated chain output tap by a digital scaling control signal indicative of a scaling coefficient, and summing circuit means for additively combining the outputs of all of the scaling circuits in the polarity relationships determined by their respective scaling coefficients, the scaling control signal generator comprising: reference signal generator means for generating a series of M DC reference signals H 1 through H M conjointly representative of the frequency response characteristic of the equalizer network in accordance with the relationship ##EQU50## multiplier means for multiplying the reference signals by a sequence of digital function data signals representative of the Fourier function series ##EQU51## in which n is the number of one stage in the all pass chain, θ is the phase shift of any signal of frequency f within the operational range of any delay stage in the chain, and θ m+1 and θ m are the phase shifts for one of the all pass delay stages at the upper and lower frequencies, respectively, of the nominal pass band for each of the delay stages to develop a series of sequences of intermediate scaling coefficient signals; and accumulator means for adding each sequence of intermediate scaling coefficient signals to generate a series of scaling control signals each representative of the scaling coefficient for one scaling circuit in the equalizer network.
Claim 57
Dependent Claim
86 words
A scaling control signal generator according to claim 53 and further comprising: digital memory means for storing the sequence of digital function data signals, the digital memory means having an output connected to the multiplier means; multiplexer means, interposed between the reference signal generator means and the multiplier means, for supplying the reference signals to the multiplier means in predetermined time sequence; and clock means connected to and actuating the multiplexer means, the digital memory means, and the accumulator means in timed coordination with each other.
Claim 58
Dependent Claim
72 words
A scaling control signal generator according to claim 54 and further comprising: reset counter means, in the clock means, for generating a reset signal, supplied to the accumulator means to terminate accumulation of each digital scaling control signal; and address counter means, in the clock means, for generating a repeating sequence of N unique address signals, with the change to the next address signal occurring in one-for-one synchronism with the reset signal.
Claim 59
Dependent Claim
52 words
A scaling control signal generator according to claim 54 in which the sequence of digital function data signals stored in the digital memory means is modified to be representative of the function series ##EQU52## for n>0, in which W(n) is a truncating function to smooth the overall frequency response of the filter.
Claim 60
Dependent Claim
12 words
A scaling control signal generator according to claim 56 in which ##EQU53##
Claim 61
Independent Claim
354 words
A method of developing the scaling coefficients to obtain a predetermined frequency response characteristic, over a preselected frequency range, from a simplified equalizer network comprising a series chain of N all pass delay stages having an initial output tap connected to the input to the first stage in the chain and N additional output taps each connected to the output of a succeeding stage in the chain, N+1 scaling circuits each connected to one of the output taps, and summing circuit means for additively combining the outputs of all of the scaling circuits in the polarity relationships determined by their respective scaling coefficients, the method comprising the following steps: A. providing an adjustable equalizer network comprising a series chain of N all pass delay stages having the same construction as the all pass chain of the simplified network, M minimum phase shift transversal filter circuits, each filter comprising N+1 scaling circuits connected to all stages of the all pass chain and an intermediate summing circuit for additively combining the filter scaling circuit outputs in predetermined polarity relationships to develop an intermediate signal in one of a series of M pass bands extending across the frequency range, and final circuit summing means for additively combining the intermediate signals to develop an equalized output signal; B. applying a "white" noise signal to the all pass chain of the adjustable equalizer network; C. adjusting the relative amplitudes of the intermediate signals to obtain the predetermined frequency response characteristic at the output of the adjustable equalizer network; D. substituting a DC reference signal input for the white noise input to the adjustable equalizer network; E. disconnecting the filter circuits of the adjustable equalizer network from all but one tap of the all pass chain for that network; F. measuring the amplitude and polarity of the DC output from the adjustable equalizer to determine the magnitude and sign of a scaling coefficient for the scaling circuit of the simplified equalizer network for that one tap of the all pass chain; and G. repeating steps E and F for each of the remaining N taps of the all pass chain.
Claim 62
Independent Claim
354 words
A method of developing the scaling coefficients to obtain a predetermined frequency response characteristic, over a preselected frequency range, from a simplified equalizer network comprising a series chain of N all pass delay stages having an initial output tap connected to the input to the first stage in the chain and N additional output taps each connected to the output of a succeeding stage in the chain, N+1 scaling circuits each connected to one of the output taps, and summing circuit means for additively combining the outputs of all of the scaling circuits in the polarity relationships determined by their respective scaling coefficients, the method comprising the following steps: A. providing an adjustable equalizer network comprising a series chain of N all pass delay stages having the same construction as the all pass chain of the simplified network, M minimum phase shift transversal filter circuits, each filter comprising N+1 scaling circuits connected to all stages of the all pass chain and an intermediate summing circuit for additively combining the filter scaling circuit outputs in predetermined polarity relationships to develop an intermediate signal in one of a series of M pass bands extending across the frequency range, and final circuit summing means for additively combining the intermediate signals to develop an equalized output signal; B. applying a "white" noise signal to the all pass chain of the adjustable equalizer network; C. adjusting the relative amplitudes of the intermediate signals to obtain the predetermined frequency response characteristic at the output of the adjustable equalizer network; D. substituting a DC reference signal input for the white noise input to the adjustable equalizer network; E. disconnecting the filter circuits of the adjustable equalizer network from all but one tap of the all pass chain for that network; F. measuring the amplitude and polarity of the DC output from the adjustable equalizer to determine the magnitude and sign of a scaling coefficient for the scaling circuit of the simplified equalizer network for that one tap of the all pass chain; and G. repeating steps E and F for each of the remaining N taps of the all pass chain.
Claim 63
Dependent Claim
110 words
The method of claim 58, in which, in step A, the M filter circuits are each provided with an initial scaling circuit having a scaling coefficient a 0 such that ##EQU54## and N additional scaling circuits each having a scaling coefficient a n such that ##EQU55## in which: n is the number of any given all pass stage in the chain, θ m+1 and θ m are the phase shifts for one of the all pass stages at the upper and lower frequencies, respectively, of the nominal frequency band for each of the M filters, and W(n) is a truncating function to smooth the overall frequency responses of the filters.
Claim 64
Dependent Claim
12 words
A method according to claim 59 in which, in step A, ##EQU56##
Claim 65
Dependent Claim
12 words
A method according to claim 60 in which, in step A, M≈N/2.
Claim 66
Dependent Claim
60 words
A method according to claim 58 in which, in step A, N is determined in accordance with the relationship ##EQU57## in which: ##EQU58## f L is the lower limit of the frequency range, f H is the upper limit of the frequency range, f H f L =f 0 2 and RC is the time constant for each delay stage.
Claim 67
Dependent Claim
110 words
The method of claim 62, in which, in step A, the M filter circuits are each provided with an initial scaling circuit having a scaling coefficient a 0 such that ##EQU59## and N additional scaling circuits each having a scaling coefficient a n such that ##EQU60## in which: n is the number of any given all pass stage in the chain, θ m+1 and θ m are the phase shifts for one of the all pass stages at the upper and lower frequencies, respectively, of the nominal frequency band for each of the M filters, and W(n) is a truncating function to smooth the overall frequency response of the filter.
Claim 68
Dependent Claim
14 words
A method according to claim 63 in which, in step A, ##EQU61## and M≈N/2.
Claim 69
Dependent Claim
52 words
A method according to claim 58 in which each step F is carried out by means of analog/digital convertor means connected to the output of the final circuit summing means for the adjustable equalizer network so that each scaling coefficient for the simplified equalizer network is developed as a digital data signal.
Claim 70
Dependent Claim
109 words
The method of claim 65, in which, in step A, the M filter circuits are each provided with an initial scaling circuit having a scaling coefficient a 0 such that ##EQU62## and N additional scaling circuits having a scaling coefficient a n such that ##EQU63## in which: n is the number of any given all pass stage in the chain, θ m+1 and θ m are the phase shifts of one of the all pass stages at the upper and lower frequencies, respectively, of the nominal frequency band for each of the M filters, and W(n) is a truncating function to smooth the overall frequency responses of the filters.
Claim 71
Dependent Claim
12 words
A method according to claim 66 in which, in step A, ##EQU64##
Claim 72
Dependent Claim
60 words
A method according to claim 67 in which, in step A, N is determined in accordance with the relationship ##EQU65## in which: ##EQU66## f L is the lower limit of the frequency range, f H is the upper limit of the frequency range, f H f L =f 0 2 and RC is the time constant for each delay stage.
Claim 73
Dependent Claim
12 words
A method according to claim 68 in which, in step A, M≈N/2.
Claim 74
Independent Claim
299 words
A method of developing the scaling coefficients to obtain a predetermined frequency response characteristic, over a preselected frequency range, from a simplified equalizer network comprising a series chain of N all pass delay stages having an initial output tap connected to the input to the first stage in the chain and N additional output taps each connected to the output of a succeeding stage in the chain, N+1 scaling circuits each connected to one of the output taps, and summing circuit means for additively combining the outputs of all of the scaling circuits in the polarity relationships determined by their respective scaling coefficients, the method comprising the following steps: A. providing a source of a series of M DC reference signals H 1 through H M conjointly representative of the frequency response characteristic of the equalizer network in accordance with the relationship ##EQU67## B. multiplying each of the signals H 1 through H M by a series of digital data signals representative of the function ##EQU68## in which n is the number of one stage in the all pass chain, θ is the phase shift of any signal of frequency f within the operational range of any delay stage in the chain, and θ m+1 and θ m are the phase shifts for one of the all pass delay stages at the upper and lower frequencies, respectively, of the nominal pass band for each of the delay stages, to develop a series of sequences of intermediate scaling coefficient signals; C. additively combining the series of signals developed in step B to generate a digital data scaling coefficient signal representative of the scaling coefficient for one scaling circuit in the equalizer network; D. and repeating steps B and C for each of the other stages of the all pass chain.
Claim 75
Independent Claim
299 words
A method of developing the scaling coefficients to obtain a predetermined frequency response characteristic, over a preselected frequency range, from a simplified equalizer network comprising a series chain of N all pass delay stages having an initial output tap connected to the input to the first stage in the chain and N additional output taps each connected to the output of a succeeding stage in the chain, N+1 scaling circuits each connected to one of the output taps, and summing circuit means for additively combining the outputs of all of the scaling circuits in the polarity relationships determined by their respective scaling coefficients, the method comprising the following steps: A. providing a source of a series of M DC reference signals H 1 through H M conjointly representative of the frequency response characteristic of the equalizer network in accordance with the relationship ##EQU67## B. multiplying each of the signals H 1 through H M by a series of digital data signals representative of the function ##EQU68## in which n is the number of one stage in the all pass chain, θ is the phase shift of any signal of frequency f within the operational range of any delay stage in the chain, and θ m+1 and θ m are the phase shifts for one of the all pass delay stages at the upper and lower frequencies, respectively, of the nominal pass band for each of the delay stages, to develop a series of sequences of intermediate scaling coefficient signals; C. additively combining the series of signals developed in step B to generate a digital data scaling coefficient signal representative of the scaling coefficient for one scaling circuit in the equalizer network; D. and repeating steps B and C for each of the other stages of the all pass chain.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-01-20 | 1989-07-22 | 1990-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-01-20 | 1993-07-22 | 1994-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-01-20 | 1997-07-22 | 1998-01-21 | $7700.00 | Window Closed / Lapsed |