Patent US3098756A successfully refreshed from Google Patents.
Patent US4564938A successfully refreshed from Google Patents.
US4564938A
Expired / Lapsed
US
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Digital electronic switching systems
Assignee: Telent Technologies Services Ltd
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Filing: 1983-09-14
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Granted: 1986-01-14
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Expires: 2003-09-14
Abstract
Abstract An electronic switching system in which digital data is required to be exchanged between two pieces of electronic apparatus such as two telephone subscribers, in which a parallel time division multiplex highway is used to carry the data, the highway being divided into two paths, the data being transferred in both directions during a single time period using the different paths for each direction, identification of the transmitting and receiving parties being by use of two address buses in a single time slot period.
Inventors
- 👤 Gordon P. Boot
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:11
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
331 words
A digital electronic switching system comprising: (A) a plurality of first and second electronic apparatus; (B) a plurality of third and fourth electronic apparatus; (C) respective first data highways interconnecting said first and said second electronic apparatus to said third and fourth electronic apparatus; and (D) a time division multiplex highway interconnecting said third and said fourth electronic apparatus; said time division multiplex highway including: (i) a first and second address bus, and (ii) a parallel data bus divided into two parallel buses for bi-directional data transfer between said third and said fourth electronic apparatus in a single time slot period of said time division multiplex highway; in which said first and said second address buses are connected to (E) a first and second address memory; said third and said fourth electronic apparatus including: (i) address decoding means responsive to addressing from said first and said second address memories via said first and said second address buses in a first time slot of said time division multiplex highway to identify particular ones of said first and said second electronic apparatus to be actuated; (ii) means to cause said particular ones of said first and said second electronic apparatus to cause data held therein to be transferred via said first highway to said third and said fourth electronic apparatus in a second time slot of said time division multiplex highway; (iii) means to cause output of the data so transferred in the second time slot to said parallel data bus in a third time slot of the time division multiplexed highway; and (iv) means to cause transfer via the first highway of the data received in the third time slot to the first and second electronic apparatus in a fourth time slot of the time division multiplex highway; said address decoding means adapted to respond to addressing during said second, third and fourth time slots and said parallel data bus adapted to carry data during said first, second and fourth time slots.
Claim 2
Dependent Claim
331 words
A digital electronic switching system comprising: (A) a plurality of first and second electronic apparatus; (B) a plurality of third and fourth electronic apparatus; (C) respective first data highways interconnecting said first and said second electronic apparatus to said third and fourth electronic apparatus; and (D) a time division multiplex highway interconnecting said third and said fourth electronic apparatus; said time division multiplex highway including: (i) a first and second address bus, and (ii) a parallel data bus divided into two parallel buses for bi-directional data transfer between said third and said fourth electronic apparatus in a single time slot period of said time division multiplex highway; in which said first and said second address buses are connected to (E) a first and second address memory; said third and said fourth electronic apparatus including: (i) address decoding means responsive to addressing from said first and said second address memories via said first and said second address buses in a first time slot of said time division multiplex highway to identify particular ones of said first and said second electronic apparatus to be actuated; (ii) means to cause said particular ones of said first and said second electronic apparatus to cause data held therein to be transferred via said first highway to said third and said fourth electronic apparatus in a second time slot of said time division multiplex highway; (iii) means to cause output of the data so transferred in the second time slot to said parallel data bus in a third time slot of the time division multiplexed highway; and (iv) means to cause transfer via the first highway of the data received in the third time slot to the first and second electronic apparatus in a fourth time slot of the time division multiplex highway; said address decoding means adapted to respond to addressing during said second, third and fourth time slots and said parallel data bus adapted to carry data during said first, second and fourth time slots.
Claim 3
Dependent Claim
87 words
A digital electronic switching system as claimed in claim 1 in which each respective connection between the first and second electronic apparatus and the third and fourth electronic apparatus includes a time division multiplex data highway divided into two parallel shelf data buses in which data is output from the first and second electronic apparatus on a first one of said two parallel shelf data buses and is input into said first and second electronic apparatus on the second one of said two parallel shelf data buses.
Claim 4
Dependent Claim
111 words
A digital electronic switching system as claimed in claim 2 in which the third and fourth electronic apparatus are identical and include a first bus driver and receiver, and receiver and driver combination for the passage of data to and from one of said parallel shelf data buses to one of said parallel data buses and a second bus driver and receiver, and receiver and driver combination for the passage of data to and from the other one of said parallel shelf data buses to the other one of said parallel data buses and in which each receiver includes storage means for storing the parallel data for one clock pulse period.
Claim 5
Dependent Claim
48 words
A digital electronic switching system as claimed in claim 3 including means for inhibiting the operation of the receivers connected to the parallel data buses when one of said first electronic apparatus connected to said third electronic apparatus is selected to transmit data onto said parallel data bus.
Claim 6
Dependent Claim
50 words
A digital electronic switching system as claimed in claim 4 in which said first and second electronic apparatus comprise telephony cards which store and forward speech stored in digital form from a first subscriber connected to said first electronic apparatus to a second subscriber connected to said second electronic apparatus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-01-13 | 1989-07-15 | 1990-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-01-13 | 1993-07-15 | 1994-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-01-13 | 1997-07-15 | 1998-01-14 | $7700.00 | Window Closed / Lapsed |