Radionavigation system having means for concealing distance and/or bearing information conveyed thereby

Claim 2

In a radionavigation system wherein a ground station includes transmission means responsive to interrogation pulses from passing aircraft for emitting outgoing signals enabling evaluating means aboard said aircraft to derive positional information from the timing thereof, the improvement wherein said ground station comprises error-generating means for introducing an artificial delay into the emission of said outgoing signals to falsify the positional information conveyed thereby, said transmission means receiving from said error-generating means a binary message representing the magnitude of said artificial delay in coded form for communication to on-board equipment of interrogating aircraft, the on-board equipment of privileged aircraft including error-eliminating means for extracting said magnitude from said binary message and controlling said evaluating means to correct the falsified positional information derived from said outgoing signals.

Claim 3

The improvement defined in claim 1 wherein said error-generating means comprises a source of randomly generated error words, first storage means for preserving over a predetermined period an original error word generated at the beginning of said period, encoding means for subjecting said original error word to a predetermined series of transformations, thereby producing a modified error word to be communicated to said on-board equipment as part of said binary message, and timing means connected to said first storage means for establishing said artificial delay under the control of said original error word; said error-eliminating means comprising decoding means complementary to said encoding means for subjecting the modified error word received with said binary message to a series of reverse transformations restoring said original error word, second storage means for temporarily preserving the restored error word, and corrective means connected to said second storage means for eliminating said artificial delay under the control of the restored error word.

Claim 4

The improvement defined in claim 2 wherein said original error word consists of a group of bits appearing in p selected positions of an original support word of n bits randomly generated by said source, with n>p, said modified error word consisting of p bits appearing in said selected positions of a distorted n-bit support word derived from said original support word by said encoding means under the control of said original error word and of the bits appearing in said selected positions after each transformation.

Claim 5

The improvement defined in claim 3 wherein said encoding means comprises a first shift register with n cyclically interconnected stages loadable by said source, a first transcoder with p inputs connected to respective stage outputs of said first shift register corresponding to said selected positions and with p outputs connected to respective first logic circuits inserted between pairs of consecutive stages of said first shift register, and first clock means for unidirectionally circulating the bits in said first shift register by one stage at a time in s successive cycles during said predetermined period with modification of bits passing through said first logic circuits in dependence upon the bits of transformed error words appearing in the p outputs of said first transcoder; said decoding means comprising a second shift register having n cyclically interconnected stages loadable with the bits of said distorted support word, a second transcoder with p inputs connected to respective stage outputs of said second shift register carrying the bits of said modified error word and with p outputs connected to respective second logic circuits inserted between pairs of consecutive stages of said second shift register, and second clock means for unidirectionally circulating the bits in said second shift register by one stage at a time in s successive cycles with modification of bits passing through said second logic circuits in dependence upon the bits of reconverted error words appearing in the p outputs of said second transcoder.

Claim 6

The improvement defined in claim 4 wherein each of said transcoders comprises a matrix with 2 p rows and 2 p columns forming 2 p junctions therebetween, a binary-decimal decoder interposed between said p inputs and said 2 p rows, and a decimal-binary coder interposed between said 2 p columns and said p outputs.

Claim 7

The improvement defined in claim 3, 4 or 5 wherein p=4.

Claim 8

The improvement defined in claim 4 or 5 wherein said logic circuits are Exclusive-OR gates.

Claim 9

The improvement defined in claim 3, 4 or 5 wherein said timing means comprises a reference oscillator, a cascade of 2 p frequency dividers connected to said reference oscillator, and a multiplexer with data inputs respectively connected to the outputs of said frequency dividers and with address inputs connected to receive the bits of said original error word contained in said first storage means.

Claim 10

The improvement defined in claim 3, 4 or 5 wherein said corrective means comprises a multiplexer with data inputs respectively connected to the outputs of 2 p frequency dividers connected in a cascade to a reference oscillator, said multiplexer having address inputs connected to receive the complement to 2 p of the restored error word contained in said second storage means.

Claim 11

The improvement defined in claim 2, 3, 4 or 5 wherein said corrective means comprises a binary subtractor connected to said evaluating means for receiving positional-information bits therefrom and diminishing the numerical value thereof by that of the restored error word contained in said second storage means.