Carry propagate adder circuit which differentially senses a carry input

Claim 2

A carry propagate adder circuit for adding first and second input bits in conjunction with an input carry bit, having sum bit generation means for receiving the first and second input bits and providing an output sum bit and having carry output bit generation means for providing a carry output bit in response to the first and second input bits and the input carry bit, comprising: first and second carry bit conductors having first and second input terminals for receiving the input carry bit and the complement thereof, respectively, and first and second output terminals for providing the carry output bit and the complement thereof, respectively; precharge means coupled to the output terminals of the carry bit conductors, for selectively charging the first and second carry bit conductors to a predetermined voltage level; and sense amplifier means having first and second inputs coupled to the first and second input terminals of the carry bit conductors, respectively, and an output coupled to the sum bit generation means, for sensing a difference in the voltage levels of the first and second carry bit conductors.

Claim 3

The carry propagate adder circuit of claim 1 wherein the precharge means further comprise: a first transistor having a first current electrode coupled to a terminal for receiving a supply voltage, a control electrode for receiving a precharge control signal, and a second current electrode coupled to the first carry bit conductor, for selectively coupling the supply voltage to the first carry bit conductor; a second transistor having a first current electrode coupled to the supply voltage, a control electrode for receiving the precharge control signal, and a second current electrode coupled to the second carry bit conductor, for selectively coupling the supply voltage to the second carry bit conductor; and a third transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode for receiving the precharge control signal, and a third current electrode coupled to the second current electrode of the second transistor, said third transistor selectively equalizing the voltage potential between the first and second carry bit conductors.

Claim 4

The carry propagate adder circuit of claim 2 wherein said first, second and third transistors are N-channel MOS transistors.

Claim 5

The carry propagate adder circuit of claim 1 wherein said sum bit generation means comprise: first logic means having first and second inputs coupled to the first and second input bits and an output; and second logic means having a first input coupled to the output of the first logic means, a second input coupled to the output of the sense amplifier means, and an output, for providing the output sum bit.

Claim 6

The carry propagate adder circuit of claim 4 wherein said carry output bit generation means comprise: third logic means having first and second inputs coupled to the first and second input bits, and an output; fourth logic means having a first input coupled to a precharge control signal, a second input coupled to the output of the first logic means, a third input coupled to the output of the third logic means, and an output; inverter means having an input coupled to the output of the third logic means, and an output; fifth logic means having a first input coupled to the output of the inverter means, a second input coupled to the output of the first logic means, a third input coupled to the precharge control signal, and an output; a first transistor having a control electrode coupled to the output of the fourth logic means, a first current electrode coupled to the output terminal of the first carry bit conductor, and a second current electrode coupled to a supply voltage, for selectively coupling the supply voltage to the output terminal of the first carry bit conductor; a second transistor having a control electrode coupled to the output of the fifth logic means, a first current electrode coupled to the output terminal of the second carry bit conductor, and a second current electrode coupled to the supply voltage, for selectively coupling the supply voltage to the output terminal of the second carry bit conductor; a third transistor having a control electrode coupled to the output of the first logic means, a first current electrode coupled to the input teminal of the first carry bit conductor, and a second current electrode coupled to the output terminal of the first carry bit conductor, for selectively coupling the input and output terminals of the first carry bit conductor; and a fourth transistor having a control electrode coupled to the output of the first logic means, a first current electrode coupled to the input terminal of the second carry bit conductor, and a second current electrode coupled to the output terminal of the second carry bit conductor, for selectively coupling the input and output terminals of the second carry bit conductor.

Claim 7

The carry propagate adder circuit of claim 5 wherein said third, fourth and fifth logic means are NOR gates.

Claim 8

The carry propagate adder circuit of claim 5 wherein said first, second, third and fourth transistors are N-channel MOS transistors.

Claim 9

The carry propagate adder circuit of claim 4 wherein said first and second logic means are exclusive OR gates.

Claim 10

The carry propagate adder circuit of claim 1 further comprising: voltage equalizing means coupled across the first and second inputs of the sense amplifier means, for selectively coupling the first and second inputs of the sense amplifier together.

Claim 11

The carry propagate adder circuit of claim 9 wherein said voltage equalizing means comprise: a transistor having a first current electrode coupled to the first input of the sense amplifier means, a second current electrode coupled to the second input of the sense amplifier means, and a control electrode coupled to a precharge control signal.