Memory circuit write-in system

Claim 1

A memory circuit write-in system comprising: terminal means for receiving a digital signal including a time base fluctuation component, one frame of said digital signal being constituted by at least a synchronizing signal and information data, said digital signal having a repetition frequency with a period of one frame of said digital signal; a memory circuit for writing therein and reading out therefrom the received digital signal; a first flip-flop which is set in response to the synchronizing signal within said received digital signal; a master oscillator for producing a signal which includes no time base fluctuation; a circuit for generating a write-in period discriminating signal, a latch pulse and a write enable signal from the output signal of said master oscillator, said write-in period discriminating signal being generated twice within one read-out frame period which is constant and substantially equal to said period of one frame, said latch pulse having a period which is less than 1/2 a minimum pulse interval of said write-in period discriminating signal; a gate circuit responsive to an output signal of said first flip-flop and to said write-in period discriminating signal for passing said write-in period discriminating signal when said first flip-flop is in a set state; and write-in control signal generating means responsive to said gate circuit for producing a write-in control signal in response to the write-in period discriminating signal which occurs immediately after said synchronizing signal, said memory circuit being controlled by said write-in control signal so that a write-in address at which the digital signal is written is changed in response to said write-in control signal, and the digital signal is written into said memory circuit during a write-in period which exists twice within the constant read-out frame period in correspondence with said write-in period discriminating signal.