Patent US4559548A successfully refreshed from Google Patents.
US4559548A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS Charge pump free of parasitic injection
Assignee: Toshiba Corp
•
Filing: 1982-04-02
•
Granted: 1985-12-17
•
Expires: 2002-04-02
Abstract
Abstract A charge pump bias generator constructed of P channel MOSFETs in an N type substrate is used to provide a negative bias to a P well containing active N-channel MOSFET circuit elements to reverse bias the N type source to P well junctions. Since the charge pump uses P channel FETs in an N substrate with the N substrate connected to the positive power supply, parasitic minority carrier injection by the charge pump is prevented.
Inventors
- 👤 Tetsuya Iizuka
- 👤 Hisashi Hara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:28
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205; H; H10; H10D; H10D89/00; H10D89/211; H10D89/213; H10D89/215
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
296 words
A substrate bias generator comprising: a semiconductor substrate; a first semiconductor region of a first conductivity type existing in said semiconductor substrate, said semiconductor region supplied with a first potential; a capacitive element formed in said first semiconductor region, said capacitive element including a second semiconductor region as a first electrode and a conductive means formed on said second semiconductor region as a second electrode with an insulation film interposed therebetween; a MOS transistor formed in said first semiconductor region serving as a first rectifying element, said MOS transistor including source and drain regions of a second conductivity type so as to establish a PN junction between said semiconductor region and said source and drain regions, said MOS transistor further including a gate electrode formed on said first semiconductor region between said source and drain regions with an insulation film interposed therebetween; a second rectifying element formed in said first semiconductor region having first and second terminals, said first terminal supplied with a second potential; a third semiconductor region of the second conductivity type existing in said semiconductor substrate, in which circuit elements are formed; voltage supply means for supplying an AC voltage to one of said first and second electrodes of said capacitive element; first means for connecting together the other one of said first and second electrodes of said capacitive element, said gate electrode of said MOS transistor, one of said source and drain regions of said MOS transistor, and said second terminal of said rectifying element; second means for connecting said third semiconductor region to the other one of said source and drain regions of said MOS transistor, whereby said PN junction formed between said first semiconductor region and said source and drain regions is reversebiased during operation of said substrate bias generator.
Claim 2
Dependent Claim
296 words
A substrate bias generator comprising: a semiconductor substrate; a first semiconductor region of a first conductivity type existing in said semiconductor substrate, said semiconductor region supplied with a first potential; a capacitive element formed in said first semiconductor region, said capacitive element including a second semiconductor region as a first electrode and a conductive means formed on said second semiconductor region as a second electrode with an insulation film interposed therebetween; a MOS transistor formed in said first semiconductor region serving as a first rectifying element, said MOS transistor including source and drain regions of a second conductivity type so as to establish a PN junction between said semiconductor region and said source and drain regions, said MOS transistor further including a gate electrode formed on said first semiconductor region between said source and drain regions with an insulation film interposed therebetween; a second rectifying element formed in said first semiconductor region having first and second terminals, said first terminal supplied with a second potential; a third semiconductor region of the second conductivity type existing in said semiconductor substrate, in which circuit elements are formed; voltage supply means for supplying an AC voltage to one of said first and second electrodes of said capacitive element; first means for connecting together the other one of said first and second electrodes of said capacitive element, said gate electrode of said MOS transistor, one of said source and drain regions of said MOS transistor, and said second terminal of said rectifying element; second means for connecting said third semiconductor region to the other one of said source and drain regions of said MOS transistor, whereby said PN junction formed between said first semiconductor region and said source and drain regions is reversebiased during operation of said substrate bias generator.
Claim 3
Dependent Claim
22 words
A substrate bias generator according to claim 1, wherein said first semiconductor region and said semiconductor substrate have the same conductivity types.
Claim 4
Dependent Claim
26 words
A substrate bias generator according to claim 2, wherein said first conductivity type is an N type and said second conductivity type is a P type.
Claim 5
Dependent Claim
21 words
A substrate bias generator according to claim 3, wherein said third semiconductor region is a P-well formed in said semiconductor substrate.
Claim 6
Dependent Claim
35 words
A substrate bias generator according to claim 1, wherein said second semiconductor region is of a second conductivity type and is integral with one of the said source and drain regions of said MOS transistor.
Claim 7
Dependent Claim
24 words
A substrate bias generator according to claim 5, wherein said AC voltage supply means is connected to said conductive means of said capacitive element.
Claim 8
Dependent Claim
53 words
A substrate bias generator according to claim 1, wherein said second rectifying element is a MOS transistor having one of said source and drain regions and a gate electrode supplied with the second reference potential, said source and drain regions being formed in said first semiconductor region and having the second conductivity type.
Claim 9
Dependent Claim
63 words
A substrate bias generator according to claim 1, wherein said second rectifying element is a diode including a fourth semiconductor region connected to said second semiconductor region of said capacitive element and one of the source and drain regions of said MOS transistor and a fifth semiconductor region of the first conductivity type, said fifth semiconductor region being supplied with the second potential.
Claim 10
Dependent Claim
30 words
A substrate bias generator according to claim 1, wherein the other one of said source and drain regions of said MOS transistor is formed integrally with said third semiconductor region.
References Cited (Backward Citations)
US4255677A
Cited
US4233672A
Cited
JPS54107128A
Cited
JPS5559757A
Cited
JPS55107255A
Cited
US4377756A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-12-16 | 1989-06-17 | 1989-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-12-16 | 1993-06-17 | 1993-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-12-16 | 1997-06-17 | 1997-12-17 | $7700.00 | Window Closed / Lapsed |