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US4559503A Expired / Lapsed US ⏱️ 0.0 years remaining

Amplifier for correcting group time delay of electrical signals and an intermediate frequency amplifier stage for radio equipment comprising an amplifier of this kind

Assignee: Alcatel Thomson Faisceaux Hertziens SA
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Filing: 1985-01-29
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Granted: 1985-12-17
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Expires: 2005-01-29
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Abstract

Abstract An amplifier for correcting group time delay of electrical signals comprises first and second DC voltage supply terminals, an input transistor to which a signal to be amplified is applied, an output transistor, a group time delay corrector network, at least one capacitor and a choke. The input and output transistors have their respective collector-emitter junctions connected in series between the first and second supply terminals. They are configured as common-emitter voltage amplifiers. The collector of the input transistor is connected to the base of the output transistor through the group time delay corrector network. The emitter of the output transistor is connected to one of the supply terminals through the capacitor and to the collector of the input transistor through the choke.

Inventors

  • 👤 Michel Camand
  • 👤 Jean-Pierre Chobert

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 20:27
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/189; H03F3/19; H04; H04B; H04B3/00; H04B3/02; H04B3/04; H04B3/14; H04B3/146; H04B3/148

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 146 words
Amplifier for correcting group time delay of electrical signals, comprising first and second DC voltage supply terminals, an input transistor having a collector, an emitter and a base and to which a signal to be amplified is applied, an output transistor having a collector, an emitter and a base, a group time delay corrector network, at least one capacitor and a choke, wherein said input and output transistors have respective collector-emitter junctions connected in series between said first and second terminals, said input and output transistors are configured as common-emitter voltage amplifiers, said collector of said input transistor is connected to said base of said output transistor through said group time delay corrector network, and said emitter of said output transistor is connected to one of said terminals through said at least one capacitor and connected to said collector of said input transistor through said choke.
Claim 2
Dependent Claim 146 words
Amplifier for correcting group time delay of electrical signals, comprising first and second DC voltage supply terminals, an input transistor having a collector, an emitter and a base and to which a signal to be amplified is applied, an output transistor having a collector, an emitter and a base, a group time delay corrector network, at least one capacitor and a choke, wherein said input and output transistors have respective collector-emitter junctions connected in series between said first and second terminals, said input and output transistors are configured as common-emitter voltage amplifiers, said collector of said input transistor is connected to said base of said output transistor through said group time delay corrector network, and said emitter of said output transistor is connected to one of said terminals through said at least one capacitor and connected to said collector of said input transistor through said choke.
Claim 3
Dependent Claim 60 words
Amplifier according to claim 1, wherein said group time delay corrector network comprises an autotransformer with a ratio of 1/2 consisting of two windings connected in series, a resistor connected between the non-commoned ends of said autotransformer windings, and an inductor and a capacitor connected in series between the commoned ends of said autotransformer windings and one of said terminals.
Claim 4
Dependent Claim 15 words
Amplifier according to claim 2, wherein said inductor and said capacitor are of variable impedance.
Claim 5
Dependent Claim 96 words
Amplifier according to claim 2, further comprising a matching circuit and wherein said group time delay corrector network has an input connected to said collector of said input transistor through said matching circuit, said output transistor has a base-emitter region, said group time delay network has an output connected to said base-emitter region, and the values Z A and Z B of the impedances of said matching circuit and said base-emitter region and the value ρ of said resistor of said group time delay corrector cell are such that |Z.sub.A |>ρ>|Z.sub.B | and 4·Z.sub.A ·Z.sub.B =ρ.sup.2.
Claim 6
Dependent Claim 39 words
Amplifier according to claim 1, further comprising a single voltage divider bridge comprising resistors connected in series between said first and second terminals and adapted to produce DC bias voltages for said bases of said input and output transistors.
Claim 7
Dependent Claim 32 words
Amplifier according to claim 1, further comprising an emitter resistor for said input transistor and wherein said emitter of said input transistor is connected to said second terminal through said emitter resistor.
Claim 8
Dependent Claim 17 words
Amplifier according to claim 6, further comprising a decoupling capacitor connected in parallel with said emitter resistor.
Claim 9
Dependent Claim 21 words
Amplifier according to claim 1, further comprising a feedback circuit connected between said collector and said base of said input transistor.
Claim 10
Dependent Claim 21 words
Amplifier according to claim 1, further comprising a feedback circuit connected between said collector and said base of said output transistor.
Claim 11
Dependent Claim 198 words
Radio amplifier stage having an input and an output and comprising a plurality of group time delay correcting amplifiers, a plurality of variable attenuators whereby said amplifiers are connected in series, and an automatic gain control circuit connected to said output of said amplifier stage and adapted to control the attenuation of said attenuators, wherein each group time delay correcting amplifier comprises first and second DC voltage supply terminals, an input transistor having a collector, an emitter and a base and to which a signal to be amplified is applied, an output transistor having a collector, an emitter and a base, a group time delay corrector network, at least one capacitor and a choke, wherein said input and output transistor have respective collector-emitter junctions connected in series between said first and second terminals, said input and output transistors are configured as common-emitter voltage amplifiers, said collector of said input transistor is connected to said base of said output transistor through said group time delay corrector network, and said emitter of said output transistor is connected to one of said terminals through said at least one capacitor and connected to said collector of said input transistor through said choke.
Claim 12
Dependent Claim 198 words
Radio amplifier stage having an input and an output and comprising a plurality of group time delay correcting amplifiers, a plurality of variable attenuators whereby said amplifiers are connected in series, and an automatic gain control circuit connected to said output of said amplifier stage and adapted to control the attenuation of said attenuators, wherein each group time delay correcting amplifier comprises first and second DC voltage supply terminals, an input transistor having a collector, an emitter and a base and to which a signal to be amplified is applied, an output transistor having a collector, an emitter and a base, a group time delay corrector network, at least one capacitor and a choke, wherein said input and output transistor have respective collector-emitter junctions connected in series between said first and second terminals, said input and output transistors are configured as common-emitter voltage amplifiers, said collector of said input transistor is connected to said base of said output transistor through said group time delay corrector network, and said emitter of said output transistor is connected to one of said terminals through said at least one capacitor and connected to said collector of said input transistor through said choke.

References Cited (Backward Citations)

DE2734945A1 Cited
SU723756A1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-12-16 1989-06-17 1989-12-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-12-16 1993-06-17 1993-12-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-12-16 1997-06-17 1997-12-17 $7700.00 Window Closed / Lapsed

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