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US4558346A Expired / Lapsed US ⏱️ 0.0 years remaining

Highly reliable hermetically sealed package for a semiconductor device

Assignee: Fujitsu Ltd
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Filing: 1983-03-23
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Granted: 1985-12-10
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Expires: 2003-03-23
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Abstract

Abstract A semiconductor device having a hermetically sealed package which includes a package substrate having a gold layer, an integrated-circuit chip attached to the gold layer, a terminal metal chip attached to the gold layer so as to ground the terminal metal chips leads, bonding wires, a cap, and glass layers for sealing the device. The terminal metal chip has a lower coating layer made of a gold-silicon type of alloy for attachment. The bond strength of the terminal metal chip is not decreased although a heat treatment is carried out to seal the glass.

Inventors

  • 👤 Susumu Kida
  • 👤 Hayato Usami
  • 👤 Hideji Aoki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 16:46
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/66; H10W72/00; H10W72/30; H10W76/00; H10W76/10; H10W76/12; H10W76/15; H10W76/157; H10W95/00; H10W70/67; H10W70/68; H10W70/682; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/541; H10W72/5449; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/90; H10W72/931; H10W72/932; H10W72/951; H10W72/952; H10W90/00; H10W90/701; H10W90/751; H10W90/754; H10W90/756; Y; Y10; Y10S; Y10S228/00; Y10S228/904; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 156 words
A semiconductor device comprising: a package substrate having a gold layer and terminal areas; an integrated circuit chip formed of silicon, attached to said gold layer and having a plurality of bonding pads formed thereon; a terminal metal chip attached to said gold layer, comprising: a metal base having first and second surfaces; an upper coating layer formed on said first surface of said metal base, of a metal selected from the group consisting of aluminum and an aluminum-silicon alloy; and a lower coating layer formed on said second surface of said metal base, made of a gold-silicon type of alloy and joined to said gold layer, said upper and lower coating layers applied to said metal base before said terminal metal chip is attached to said gold layer; and bonding wires electrically connecting said terminal areas to said upper coating layer of said terminal metal chip and to said bonding pads of said integrated-circuit chip.
Claim 2
Dependent Claim 156 words
A semiconductor device comprising: a package substrate having a gold layer and terminal areas; an integrated circuit chip formed of silicon, attached to said gold layer and having a plurality of bonding pads formed thereon; a terminal metal chip attached to said gold layer, comprising: a metal base having first and second surfaces; an upper coating layer formed on said first surface of said metal base, of a metal selected from the group consisting of aluminum and an aluminum-silicon alloy; and a lower coating layer formed on said second surface of said metal base, made of a gold-silicon type of alloy and joined to said gold layer, said upper and lower coating layers applied to said metal base before said terminal metal chip is attached to said gold layer; and bonding wires electrically connecting said terminal areas to said upper coating layer of said terminal metal chip and to said bonding pads of said integrated-circuit chip.
Claim 3
Dependent Claim 29 words
A semiconductor device according to claim 1, wherein said metal base is made of a metal selected from the group consisting of an iron-nickel-cobalt alloy and an iron-nickel alloy.
Claim 4
Dependent Claim 29 words
A semiconductor device according to claim 1, wherein said gold-silicon type of alloy is a metal selected from the group consisting of a gold-silicon alloy and a gold-germanium-silicon alloy.
Claim 5
Dependent Claim 73 words
A terminal connected to an integrated circuit device comprising: a metal base having first and second surfaces; an upper coating layer, formed on said first surface of said metal base, of a metal selected from the group consisting of aluminum and an aluminum silicon alloy; and a lower coating layer, formed on said second surface of said metal base and operatively connected to the integrated circuit device, of a gold-silicon type of alloy.
Claim 6
Dependent Claim 73 words
A terminal connected to an integrated circuit device comprising: a metal base having first and second surfaces; an upper coating layer, formed on said first surface of said metal base, of a metal selected from the group consisting of aluminum and an aluminum silicon alloy; and a lower coating layer, formed on said second surface of said metal base and operatively connected to the integrated circuit device, of a gold-silicon type of alloy.
Claim 7
Dependent Claim 15 words
A terminal according to claim 4, wherein said metal base is approximately 0.5 mm thick.
Claim 8
Dependent Claim 20 words
A terminal according to claim 4, wherein said upper coating layer has a thickness of from 5 to 15 μm.
Claim 9
Dependent Claim 20 words
A terminal according to claim 4, wherein said lower coating layer has a thickness of from 25 to 35 μm.

References Cited (Backward Citations)

JPS5527615A Cited
JPS55153341A Cited
JPS5854644A Cited
US4447857A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-12-09 1989-06-10 1989-12-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-12-09 1993-06-10 1993-12-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-12-09 1997-06-10 1997-12-10 $7700.00 Window Closed / Lapsed

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