← Back to Patent Explorer
US4447857A Expired / Lapsed US ⏱️ 0.0 years remaining

Substrate with multiple type connections

Assignee: International Business Machines Corp
•
Filing: 1981-12-09
•
Granted: 1984-05-08
•
Expires: 2001-12-09
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A novel substrate is disclosed which can mount either flip-chip solder bonded IC chips or wire bonded chips, or both chips, or a single chip having both solder bonds and wire bonds is disclosed. The substrate has an array of solder pads which will accept solder bonds. Those pads which are to be used for wire bonding have mounted thereon a trimetallic pedestal. Each pedestal has a layer of solder metal bonded to the solder pad, a top layer metal suitable for wire bonding, such as, aluminum or gold, and an intermediate layer of metal, such as nickel, which is impervious to both solder metal and the top layer metal.

Inventors

  • 👤 Robert Marks
  • 👤 Douglas W. Phelps, Jr.
  • 👤 William C. Ward

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 15:59
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/40; H05K3/4007; H05K3/4015; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W99/00; H10W72/00; H10W72/071; H10W72/075; H10W72/07511; H10W72/07531; H10W72/07532; H10W72/07533; H10W72/50; H10W72/541; H10W72/5434; H10W72/5445; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/59; H10W72/851; H10W72/874; H10W72/879; H10W72/884; H10W72/90; H10W72/951; H10W72/952; H10W90/00; H10W90/701; H10W90/721; H10W90/724; H10W90/731; H10W90/734; H10W90/751; H10W90/753; H10W90/754

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 295 words
A package for semiconductor integrated circuits comprising: a substrate having input/output means; a plurality of solder pads on said substrate; at least one integrated circuit chip having its back surface attached to said substrate in a face-up configuration with contact pad metal adapted to receive wire bond type connections; at least one of said solder pads on said substrate having a multi-layer metallic pedestal thereon, said multi-layer metallic pedestal having a solder layer joined to said at least one solder pad, an upper layer of said pedestal made of the same metal as said contact pad metal and adapted to receive wire bond type connections, and a barrier layer of metal interposed between said solder layer and said upper layer, said barrier layer being substantially impervious to both solder and the metal of said upper layer; a wire formed from the same metal as the contact pad metal and said upper layer, bonded thereto to form a high temperature sustaining wire bond connection between the contact pad metal on the face-up integrated circuit chip and the multi-layer metallic pedestal on the substrate; a predetermined number of said solder pads arranged in a pattern for interconnecting at least one integrated circuit chip to said substrate in a flip-chip configuration; at least one integrated circuit chip attached to said substrate in a flip-chip configuration by means of said predetermined number of solder pads which are arranged for interconnecting integrated circuit chips in a flip-chip configuration; interconnecting conductor lines on said substrate for providing electrical connections between a preselected number of said solder pads which are connecting an integrated circuit chip to said substrate in a face-up configuration and a preselected number of said solder pads connecting an integrated circuit chip to said substrate in a flip-chip configuration.
Claim 2
Dependent Claim 295 words
A package for semiconductor integrated circuits comprising: a substrate having input/output means; a plurality of solder pads on said substrate; at least one integrated circuit chip having its back surface attached to said substrate in a face-up configuration with contact pad metal adapted to receive wire bond type connections; at least one of said solder pads on said substrate having a multi-layer metallic pedestal thereon, said multi-layer metallic pedestal having a solder layer joined to said at least one solder pad, an upper layer of said pedestal made of the same metal as said contact pad metal and adapted to receive wire bond type connections, and a barrier layer of metal interposed between said solder layer and said upper layer, said barrier layer being substantially impervious to both solder and the metal of said upper layer; a wire formed from the same metal as the contact pad metal and said upper layer, bonded thereto to form a high temperature sustaining wire bond connection between the contact pad metal on the face-up integrated circuit chip and the multi-layer metallic pedestal on the substrate; a predetermined number of said solder pads arranged in a pattern for interconnecting at least one integrated circuit chip to said substrate in a flip-chip configuration; at least one integrated circuit chip attached to said substrate in a flip-chip configuration by means of said predetermined number of solder pads which are arranged for interconnecting integrated circuit chips in a flip-chip configuration; interconnecting conductor lines on said substrate for providing electrical connections between a preselected number of said solder pads which are connecting an integrated circuit chip to said substrate in a face-up configuration and a preselected number of said solder pads connecting an integrated circuit chip to said substrate in a flip-chip configuration.
Claim 3
Dependent Claim 52 words
A package for semiconductor integrated circuits as in claim 1 wherein the high temperature sustaining wire bond connection is a mono-metallic system comprising: an aluminum wire bonded to an aluminum contact pad metal on the face-up integrated circuit chip, and also bonded to an aluminum upper layer of said multi-layer metallic pedestal.
Claim 4
Dependent Claim 50 words
A package for semiconductor integrated circuits as in claim 1 wherein the high temperature sustaining connection is a mono-metallic system comprising: a gold wire bonded to a gold contact pad metal on the face-up integrated circuit chip, and also bonded to a gold upper layer of said multi-layer metallic pedestal.
Claim 5
Dependent Claim 31 words
A package for semiconductor integrated circuits as in claim 1 where said barrier layer comprises metal selected from the group consisting of nickel, nickel alloys, copper, copper alloys, and stainless steel.

References Cited (Backward Citations)

US3544704A Cited
US3591839A Cited
US3770874A Cited
US3778530A Cited
US3809797A Cited
US3781596A Cited
US4074342A Cited
US4145120A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-05-08 1987-11-07 1988-05-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-05-08 1991-11-07 1992-05-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-05-08 1995-11-07 1996-05-08 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag