Address sequencer for overwrite avoidance

Claim 2

Apparatus for providing a sequence of address signals to an addressing means of a digital computer, wherein said addressing means accesses locations in memory of said digital computer, comprising: address index input register for accepting an address index input and for providing a first signal comprising n-k bits and a second signal comprising k bits, linear code sequence means for accepting said second signal and for generating a sequence of n dimensional binary words, said sequence comprising a repeating cycle of 2 k linear (n, k, d) code words, each linear code word comprising k data bits and n-k check bits, said k data bits occupying the same positions in each linear code word; Gray code sequence means for accepting said first signal and for generating a sequence of n-k dimensional binary words, said sequence of n-k dimensional binary words comprising words of a Gray code of dimension n-k, an individual Gray code word occurring consecutively 2 k times, and distinct Gray code words occurring in the order in which they appear in said Gray code; zero filler means for generating a sequence of k dimensional binary words, each of said k dimensional binary words comprising k zero bits; and Exclusive-OR additional means, coupled to receive said linear code sequence means generated n-dimensional binary words, said Gray code sequence means generated n-k dimensional binary words and said zero filler means generated k dimensional binary words for performing Exclusive-OR addition of the members of said sequence of n-k dimensional binary words to, respectively, said n-k check bits of the members of said sequence of n dimensional binary words, and for performing Exclusive-OR addition of the members of said sequence of k dimensional binary words to, respectively, said k data bits of the members of said sequence of n dimensional binary words, output of said Exclusive-OR addition means comprises said sequence of address signals whereby said address signals are applied to said addressing means for accessing said locations of said memory in accordance with said address signals.

Claim 3

An apparatus as in claim 1 wherein said linear code sequence means comprises a linear (n, k, d) coder.

Claim 4

An apparatus as in claim 1 wherein said Gray code sequence means comprises an n-k dimensional Gray coder.

Claim 5

An apparatus as in claim 1 wherein said Exclusive-OR addition means comprises n Exclusive-OR gates.

Claim 6

An apparatus as in claim 2 wherein said Gray code sequence means comprises an n-k dimensional Gray coder.

Claim 7

An apparatus as in claim 5 wherein said Exclusive-OR addition means comprises n Exclusive-OR gates.

Claim 8

An apparatus as in claim 1 wherein said linear (n, k, d) code is a (16, 11, 4) extended Hamming code.

Claim 9

An apparatus as in claim 6 wherein said linear (n, k, d) code is a (16, 11, 4) extended Hamming code.

Claim 10

An apparatus as in claim 1 wherein said linear (n, k, d) code is a (24, 12, 8) extended Golay code.

Claim 11

An apparatus as in claim 6 wherein said linear (n, k, d) code is a (24, 12, 8) extended Golay code.

Claim 12

An apparatus as in claim 1 wherein said linear (n, k, d) code is an (n, n-10, 5) BCH code where 24≦n≦32.

Claim 13

An apparatus as in claim 6 wherein said linear (n, k, d) code is an (n, n-10, 5) BCH code where 24≦n≦32.

Claim 14

Apparatus for providing a sequence of address signals to an addressing means of a digital computer, wherein said addressing means accesses locations in memory of said digital computer, comprising: address index input register means for sequentially loading with address indices in consecutive order in n dimensional binary equivalent word form with a higher order n-k bits and a lower order k bits and for providing a first signal of higher order n-k bits and a second signal of lower order k bits, linear coder means, coupled to said register means, for accepting said second signal and for generating a sequence of linear (n, k, d) code words from the lower order k register bits of said indices, by utilizing said lower order k register bits of individual address indices as k data bits to which n-k generated check bits are appended to form corresponding linear (n, k, d) code words, said k data bits occupying the same positions in each linear (n, k, d) code word; Gray coder means, coupled to said register means, for accepting said first signal and for generating a sequence comprising words of a Gray code of dimension n-k, by utilizing the higher order n-k register bits of individual address indices to generate a corresponding Gray code word; zero filler means for generating a sequence of k dimensional binary words, each of said K dimensional binary words comprising K zero bits; and Exclusive-OR addition means, coupled to receive said linear coder means generated code words, said Gray coder means generated code words and said zero filler means generated binary words for performing Exclusive-OR addition of the members of said sequence comprising words of a Gray code of dimensions n-k to, respectively, said n-k check bits of the members of said sequence of linear (n, k, d) code words, and for performing Exclusive-OR addition of the members of said sequence of k dimensional binary words to, respectively, said k data bits of the members of said sequence of linear (n, k, d) code words, output of said Exclusive-OR addition comprises said sequence of address signals whereby said address signals are means applied to said addressing means for accessing said locations of said memory in accordance with said address signals.

Claim 15

Apparatus for providing a sequence of address signals to an addressing means of a digital computer, wherein said addressing means accesses locations in memory of said digital computer, comprising: address index input register means for sequentially loading with address indices in consecutive order in n dimensional binary equivalent word form with a higher order n-k bits and a lower order k bits and for providing a first signal of higher order n-k bits and a second signal of lower order k bits, linear coder means, coupled to said register means, for accepting said second signal and for generating a sequence of linear (n, k, d) code words from the lower order k register bits of said indices, by utilizing said lower order k register bits of individual address indices as k data bits to which n-k generated check bits are appended to form corresponding linear (n, k, d) code words, said k data bits occupying the same positions in each linear (n, k, d) code word; Gray coder means, coupled to said register means, for accepting said first signal and for generating a sequence comprising words of a Gray code of dimension n-k, by utilizing the higher order n-k register bits of individual address indices to generate a corresponding Gray code word; zero filler means for generating a sequence of k dimensional binary words, each of said K dimensional binary words comprising K zero bits; and Exclusive-OR addition means, coupled to receive said linear coder means generated code words, said Gray coder means generated code words and said zero filler means generated binary words for performing Exclusive-OR addition of the members of said sequence comprising words of a Gray code of dimensions n-k to, respectively, said n-k check bits of the members of said sequence of linear (n, k, d) code words, and for performing Exclusive-OR addition of the members of said sequence of k dimensional binary words to, respectively, said k data bits of the members of said sequence of linear (n, k, d) code words, output of said Exclusive-OR addition comprises said sequence of address signals whereby said address signals are means applied to said addressing means for accessing said locations of said memory in accordance with said address signals.

Claim 16

An apparatus as in claim 13 wherein said linear coder means comprises a linear (n, k, d) coder.

Claim 17

An apparatus as in claim 13 wherein said Gray coder means comprises an n-k dimensional Gray coder.

Claim 18

An apparatus as in claim 13 wherein said Exclusive-OR additional means comprises n Exclusive-OR gates.

Claim 19

An apparatus as in claim 14 wherein said Gray coder means comprises an n-k dimensional Gray coder.

Claim 20

An apparatus as in claim 17 wherein said Exclusive-OR addition means comprises n Exclusive-OR gates.

Claim 21

An apparatus as in claim 13 wherein said linear (n, k, d) code comprises a (16, 11, 4) extended Hamming code.

Claim 22

An apparatus as in claim 18 wherein said linear (n, k, d) code comprises a (16, 11, 4) extended Hamming code.

Claim 23

An apparatus as in claim 13 wherein said linear (n, k, d) code comprises a (24, 12, 8) extended Golay Code.

Claim 24

An apparatus as in claim 18 wherein said linear (n, k, d) code comprises a (24, 12, 8) extended Golay code.

Claim 25

An apparatus as in claim 13 wherein said linear (n, k, d) code comprises an (n, n-10, 5) BCH code where 24 ≦n≦32.

Claim 26

An apparatus as in claim 18 wherein said linear (n, k, d) code comprises an (n, n-10, 5) BCH code where 24≦n≦32.