US4556909A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Solid state image sensing device having a number of static induction transistors arranged in a matrix form
Assignee: Olympus Corp
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Filing: 1984-09-04
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Granted: 1985-12-03
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Expires: 2004-09-04
Abstract
Abstract A solid state image sensing device having a number of static induction transistors (SIT) arranged in a matrix form, sources of SITs arranged in each column being commonly connected to respective column line which is connected to a video line via respective column selection transistor whose gate is connected to a horizontal scanning circuit, gates of SITs arranged in each row being connected to respective row line connected to a vertical scanning circuit, and drains of all the SITs being commonly connected to the ground. The vertical scanning circuit produces a row selection signal which has such a potential that an SIT is readout, while its gate is biased reversely.
Inventors
- 👤 Hidetoshi Yamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:31
CPC Classifications
H; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/196; H04; H04N; H04N25/00; H04N25/70; H04N25/76; H04N25/779; H10F30/00; H10F30/20; H10F30/21; H10F30/28; H10F30/285; H10F30/2863
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
115 words
A solid state image sensing device comprising a plurality of row lines; a plurality of column lines; means for applying row selection signals successively to said row lines; means for applying column selection signals successively to said column lines; a plurality of pixels arranged in a matrix form, each comprising a static induction transistor having one main electrode region connected to a column line, the other main electrode region connected commonly, a channel region disposed between said main electrode regions and a gate electrode region, and a capacitance connected between the gate electrode region and a row line; and means for biasing reversely said gate electrode region at the time of reading out said pixel.
Claim 2
Dependent Claim
115 words
A solid state image sensing device comprising a plurality of row lines; a plurality of column lines; means for applying row selection signals successively to said row lines; means for applying column selection signals successively to said column lines; a plurality of pixels arranged in a matrix form, each comprising a static induction transistor having one main electrode region connected to a column line, the other main electrode region connected commonly, a channel region disposed between said main electrode regions and a gate electrode region, and a capacitance connected between the gate electrode region and a row line; and means for biasing reversely said gate electrode region at the time of reading out said pixel.
Claim 3
Dependent Claim
57 words
A device according to claim 1, wherein said biasing means is so constructed that it produces a row selection signal which has a potential for reading out the pixel while the gate electrode region is biased reversely, and the device further comprises means for resetting a potential of the gate electrode region after the pixel is readout.
Claim 4
Dependent Claim
33 words
A device according to claim 2, wherein said resetting means is so constructed that it produces a reset signal for biasing the gate electrode region forwardly, after the row selection signal is produced.
Claim 5
Dependent Claim
39 words
A device according to claim 2, wherein said resetting means applies to one of the main electrode regions a potential for forwardly biasing a pn junction between the gate electrode region and said one of the main electrode region.
Claim 6
Dependent Claim
20 words
A device according to claim 1, wherein said static induction transistor is formed by a normally-on type static induction transistor.
Claim 7
Dependent Claim
69 words
A device according to claim 3, wherein said column selection signal applying means comprises a plurality of column selection transistors, each having a first main electrode connected to respective one of the column lines, a second main electrode connected commonly to a video line and a gate electrode, and a horizontal scanning circuit having outputs each connected to the gate electrode of respective one of the column selection transistors.
Claim 8
Dependent Claim
46 words
A device according to claim 6, wherein said video line is connected to one terminal of a voltage supply source whose other terminal is connected to the ground and said other main electrode regions of all the static induction transistors are commonly connected to the ground.
Claim 9
Dependent Claim
43 words
A device according to claim 6, wherein said video line is connected to the ground via a load resistor and said other main electrode regions are connected to one terminal of a voltage supply source whose other terminal is connected to the ground.
Claim 10
Dependent Claim
74 words
A device according to claim 6, wherein resetting means comprises a plurality of resetting transistors each having a first main electrode connected to respective one of the column lines, a second main electrode connected commonly to a reset bias voltage supply source and a gate connected to an output of the horizontal scanning circuit, which output is also connected to a gate of a column selection transistor connected to a next succeeding column line.
Claim 11
Dependent Claim
31 words
A device according to claim 6, wherein said resetting means comprises a resetting circuit whose output is commonly connected to the other main electrode regions of all the static induction transistors.
Claim 12
Dependent Claim
59 words
A device according to claim 6, wherein said resetting means comprises a plurality of resetting transistors, each having a first main electrode connected to respective one of the column lines, a second main electrode connected to a reference potential and a gate, and a reset control circuit having an output connected commonly to the gates of said resetting transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-12-02 | 1989-06-03 | 1989-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-12-02 | 1993-06-03 | 1993-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-12-02 | 1997-06-03 | 1997-12-03 | $7700.00 | Window Closed / Lapsed |