Patent US4556905A successfully refreshed from Google Patents.
US4556905A
Expired / Lapsed
US
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Vertical synchronizing control circuit
Assignee: Suwa Seikosha KK
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Filing: 1983-11-10
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Granted: 1985-12-03
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Expires: 2003-11-10
Abstract
Abstract After an external vertical sync signal is inputted, a divider circuit counts a predetermined number of clock pulses and delivers a vertical sync signal and a control signal allowing the external signal to pass through a gate circuit. The external vertical sync signal passing through the gate circuit resets the counter and a control signal from a detector circuit blocks the gate circuit until the counter delivers the next control signal. The divider circuit delivers a vertical sync pulse with proper timing and resets itself if the external signal is weak or absent.
Inventors
- 👤 Hiroaki Ikejiri
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:59
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/06; H04N5/067; H04N5/073; H04N5/08; H04N5/12
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
252 words
A vertical synchronizing control circuit receiving an external vertical sync signal, comprising: a vertical sync control signal forming circuit having counter means counting an inputted clock signal and delivering in response to said counting a first control signal and a vertical sync control signal, said control signals having the same frequency as said external vertical sync signal, said control signal forming circuit having a first control terminal and circuit means for synchronizing said vertical sync control signal with said external vertical sync signal; gate circuit means for controlling passage of said external vertical sync signal, said gate circuit means having a second control terminal which when driven by said first control signal allows said external vertical sync signal to pass through said gate circuit means, and a third control terminal which when driven inhibits said external vertical sync signal from passing; a detector circuit for detecting the passing of said external vertical sync signal through said gate circuit, said detector circuit delivering a second control signal when said external vertical sync signal is detected passing said gate circuit means, said second control signal being applied to said third control terminal to block said gate circuit means, said circuit means for synchronizing said vertical sync control signal being input said external vertical sync signal passing through said gate circuit means at said first control terminal of said vertical sync control signal forming circuit, noise in said external signal being excluded from said circuit means for synchronizing when said gate circuit means is blocked.
Claim 2
Dependent Claim
252 words
A vertical synchronizing control circuit receiving an external vertical sync signal, comprising: a vertical sync control signal forming circuit having counter means counting an inputted clock signal and delivering in response to said counting a first control signal and a vertical sync control signal, said control signals having the same frequency as said external vertical sync signal, said control signal forming circuit having a first control terminal and circuit means for synchronizing said vertical sync control signal with said external vertical sync signal; gate circuit means for controlling passage of said external vertical sync signal, said gate circuit means having a second control terminal which when driven by said first control signal allows said external vertical sync signal to pass through said gate circuit means, and a third control terminal which when driven inhibits said external vertical sync signal from passing; a detector circuit for detecting the passing of said external vertical sync signal through said gate circuit, said detector circuit delivering a second control signal when said external vertical sync signal is detected passing said gate circuit means, said second control signal being applied to said third control terminal to block said gate circuit means, said circuit means for synchronizing said vertical sync control signal being input said external vertical sync signal passing through said gate circuit means at said first control terminal of said vertical sync control signal forming circuit, noise in said external signal being excluded from said circuit means for synchronizing when said gate circuit means is blocked.
Claim 3
Dependent Claim
62 words
A vertical synchronizing control circuit as claimed in claim 1, wherein said second control signal follows said first control signal in time, said second control signal blocking said gate circuit means to said external signal after said first control signal has opened said gate circuit means to said external signal, said gate circuit means being reopened by the next first control signal.
Claim 4
Dependent Claim
39 words
A vertical synchronizing control circuit as claimed in claim 2, wherein said circuit means for synchronizing operates to reset said counter means at input at said first control terminal of said external sync signal from said gate circuit means.
Claim 5
Dependent Claim
75 words
A vertical synchronizing control circuit as claimed in claim 3, and further comprising means for resetting said counter means in response to a preselected count of said counter means, said preselected count corresponding to the period of said external vertical sync signal, occurrence of said preselected count causing output of first control signal and said counter means to reset even should said external vertical sync signal from said gate circuit means be weak or absent.
Claim 6
Dependent Claim
51 words
A vertical synchronizing control circuit as claimed in claim 1, wherein said gate circuit means includes a set-reset circuit, said first control signal setting said set-reset circuit, said second control signal resetting said set-reset circuit, the output of said gate circuit means changing only for alternating first and second control signals.
Claim 7
Dependent Claim
43 words
A vertical synchronizing control circuit as claimed in claim 1, wherein said detector circuit includes a delay type flipflop, the output of said detector circuit being later than the leading edge of said external vertical sync signal passed through said gate circuit means.
Claim 8
Dependent Claim
43 words
A vertical synchronizing control circuit as claimed in claim 5, wherein said detector circuit includes a delay type flipflop the output of said detector circuit being later than the leading edge of said external vertical sync signal passed through said gate circuit means.
Claim 9
Dependent Claim
43 words
A vertical synchronizing control circuit as claimed in claim 1, wherein said circuit means for synchronizing includes an OR gate, one input to said OR gate being connected to said first control terminal the output of said OR gate resetting said counter means.
Claim 10
Dependent Claim
30 words
A vertical synchronizing control circuit as claimed in claim 1, wherein said detector output corresponds with the trailing edge of said external sync signal passing through said gate circuit means.
Claim 11
Dependent Claim
65 words
A vertical synchronizing control circuit as claimed in claim 8, wherein an input to a second terminal of said OR gate corresponds to an output from said counter means in response to a preselected count of said counter means, a signal to either of said OR gate inputs resetting said counter means, said preselected count corresponding to the frequency of said external vertical sync signal.
Claim 12
Dependent Claim
32 words
A vertical synchronizing control circuit as claimed in claim 10, wherein said vertical sync control signal is delivered from said forming circuit upon completion of said preselected count by said counter means.
Claim 13
Dependent Claim
84 words
A vertical synchronizing control circuit as claimed in claim 4, wherein said gate circuit means includes a set-reset circuit, said first control signal setting said set-reset circuit, said second control signal resetting said set-reset circuit, the output of said gate circuit means changing only for alternating first and second control signals, and said detector circuit includes a delay type flip-flop, the output of said detector circuit being later than the leading edge of said external vertical sync signal passed through said gate circuit means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-12-02 | 1989-06-03 | 1989-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-12-02 | 1993-06-03 | 1993-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-12-02 | 1997-06-03 | 1997-12-03 | $7700.00 | Window Closed / Lapsed |