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US4555783A
Expired / Lapsed
US
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Method of computerized in-circuit testing of electrical components and the like with automatic spurious signal suppression
Assignee: Genrad Inc
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Filing: 1982-04-30
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Granted: 1985-11-26
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Expires: 2002-04-30
Abstract
Abstract This disclosure is concerned with suppressing spurious signals generated during the in-circuit testing of circuit components, and which spurious signals may interfere with test signals being forced at selected nodes of the circuit that are inputs to components being tested and wherein such spurious signals may be routed via certain of the other circuit components, by automatically inhibiting either potential transmission of spurious signals by applying specific signals to components identified by analysis as normally feeding or processing input signals to the component(s) under test, or automatically inhibiting all inhibitable input parts of all components identified as those capable of passing such spurious signals to the input of the component(s) under test.
Inventors
- 👤 Mark Swanson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:52
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31915
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
155 words
A method of computerized in-circuit testing of components in circuit boards and the like, that comprises, forcing test signals under computer program control at selected nodes of the circuit that are inputs of the components thereof, effectively to isolate such components from the circuit and enable testing thereof as though such were not a part of the circuit; and suppressing possible spurious signals generated during such testing including the routing by the circuit of an output signal of a component under test via feedback paths to the input in interference with the forcing test signal and other spurious signal sources and paths shared by components, by: (a) identifying circuit components feeding or processing input signals to the component(s) under test and that can pass said spurious signals; and (b) automatically inhibiting potential transmission of spurious signals by applying specific signals to the identified components prior to or during the testing of the component(s) under test.
Claim 2
Independent Claim
155 words
A method of computerized in-circuit testing of components in circuit boards and the like, that comprises, forcing test signals under computer program control at selected nodes of the circuit that are inputs of the components thereof, effectively to isolate such components from the circuit and enable testing thereof as though such were not a part of the circuit; and suppressing possible spurious signals generated during such testing including the routing by the circuit of an output signal of a component under test via feedback paths to the input in interference with the forcing test signal and other spurious signal sources and paths shared by components, by: (a) identifying circuit components feeding or processing input signals to the component(s) under test and that can pass said spurious signals; and (b) automatically inhibiting potential transmission of spurious signals by applying specific signals to the identified components prior to or during the testing of the component(s) under test.
Claim 3
Dependent Claim
80 words
A method as claimed in claim 1 and in which said step of identifying circuit components is effected by identifying those components that normally feed or process input signals to the component(s) under test, including those that may feed back signals from the components(s) under test, and thus are the components that can pass said spurious signals; and said step of automatically inhibiting potential transmission of spurious signals by application of specific signals is effected for the identified components only.
Claim 4
Dependent Claim
116 words
A method as claimed in claim 1 and in which said step of identifying circuit components is effected by identifying all components that are capable of feeding or processing input signals to the component(s) under test and are thus potential components for the conveying of said spurious signals; and said step of automatically inhibiting is effected by inhibiting all inhibitable spurious-signal input paths to the circuit under test by application of specific signals to the identified components irrespective of the potential of said identified components for being part of a source of said spurious signals; and eliminating the effect of said spurious signals without the necessity for analyzing the circuit for sources of said spurious signals.
Claim 5
Dependent Claim
26 words
A method as claimed in claim 1 and in which said inhibiting is effected by driving the inputs to the identified components to an inhibit state.
Claim 6
Dependent Claim
77 words
A method as claimed in claim 4 and in which the program for effecting said testing is stored in a test library, and the inhibit states for inhibiting said identified component inputs are also thusly stored so that the same do not have to be identified each time a new circuit test is developed, but such new test is assembled from the said library following identifying the components to be inhibited as part of the assembly process.
Claim 7
Dependent Claim
41 words
A method as claimed in claim 5 and in which said identifying and driving steps comprise identifying how to inhibit signal propagation for each component, and then applying the same to all components which drive inputs of the component under test.
Claim 8
Dependent Claim
17 words
A method as claimed in claim 6 and in which said component may comprise integrated circuit components.
Claim 9
Dependent Claim
34 words
A method as claimed in claim 6 and in which said inputs comprise an AND gate or the like and the inhibiting is effected by placing other inputs in a low or false state.
Claim 10
Dependent Claim
21 words
A method as claimed in claim 6 and in which said testing is one or both of digital and analog testing.
Claim 11
Independent Claim
112 words
A method of suppressing spurious signals generated during the in-circuit testing of circuit components, and in which spurious signals may interefere with test signals being forced at selected nodes of the circuit that are inputs to components being tested, wherein such spurious signals may be routed via certain of the other circuit components, said method comprising automatically inhibiting either potential transmission of spurious signals by applying specific signals to components identified by analysis as normally feeding or processing input signals to the component(s) under test, or automatically inhibiting all inhibitable input parts of all components identified as those capable of passing such spurious signals to the input of the component(s) under test.
Claim 12
Independent Claim
112 words
A method of suppressing spurious signals generated during the in-circuit testing of circuit components, and in which spurious signals may interefere with test signals being forced at selected nodes of the circuit that are inputs to components being tested, wherein such spurious signals may be routed via certain of the other circuit components, said method comprising automatically inhibiting either potential transmission of spurious signals by applying specific signals to components identified by analysis as normally feeding or processing input signals to the component(s) under test, or automatically inhibiting all inhibitable input parts of all components identified as those capable of passing such spurious signals to the input of the component(s) under test.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-11-25 | 1989-05-27 | 1989-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-11-25 | 1993-05-27 | 1993-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-11-25 | 1997-05-27 | 1997-11-26 | $7700.00 | Window Closed / Lapsed |