Low stress leadless chip carrier and method of assembly

Claim 1

An integrated circuit chip carrier for mounting and electrically connecting the integrated circuit chip to a printed circuit board conductor pattern, which carrier comprises a leadless carrier member having a conductive path disposed on a top surface with the integrated circuit chip mounted on this top surface with chip contacts electrically connected to the conductive path, and wherein a plurality of castellations are provided in the perimeter walls of the carrier with reflowed solder conductor means extending along the castellated perimeter wall portions and electrically connecting the carrier top surface conductive path with the printed circuit board conductor pattern and a spacer member is disposed between the under surface of the leadless carrier member and the printed circuit board, which spacer member comprises a high thermal conductivity planar metal portion sandwiched between adhesive insulating layers on either side of the planar metal portion which spacer member is about 0.015 inch thick, with solder connections extending between the printed circuit board and the carrier castellations, with the thermal expansion coefficient for the spacer matched to that of the solder and the thickness of the spacer member defining a solder connection height providing a low stress solder connection.