Flag detection circuit

Claim 1

A flag detection circuit for detecting the binary flag "01111110" serially transmitted through a telecommunication channel, comprising: receiving means for receiving serial digital bits from said telecommunication channel; clock means for providing clock pulses synchronized with said digital signals; an octal shift register arranged with said receiver means and said clock means for storing the eight most recent consecutive bits from said telecommunication channel and having an eight bit output at which the eight stored bits appear in parallel; a NAND gate having an eight bit input coupled to the eight bit output of said octal shift register and having an output; said eight bit input has a most significant bit input and a least significant bit input; a first inverter interposed in the most signifcant bit input of said NAND gate; and a second inverter interposed in the least significant bit input of said NAND gate; said NAND gate arranged to provide a logic "0" output upon the presence of all "1" inputs. a latched gate having an input coupled to the output of said NAND gate; and a delay circuit interposed between said clock means and said latched gate for delaying said clock pulses; said latched gate having an output arranged to provide a logic "1" at said output of said latched gate upon the presence of a logic "0" input and a delayed clock pulse, said logic "1" indicative of a detected flag.