Signal transition enhancement circuit

Claim 2

A signal processing circuit comprising: an input for receiving input signals and an output at which output signals responsive to said input signals are produced; a plurality of delaying means coupled in cascade between said input and said output for successively delaying said input signals; detecting means, coupled to said plurality of delaying means and responsive to ones of said successively delayed input signals, for detecting a magnitude transition of said input signals; and means, coupled to said plurality of delaying means and to said detecting means, for selectively coupling an input of one of said delaying means to an input of another one of said delaying means in response to said detecting of said magnitude transition.

Claim 3

The circuit of claim 1 wherein said one of said delaying means is more proximate said input than is said other one of said delaying means.

Claim 4

The circuit of claim 1 wherein said one of said delaying means is more proximate said output than is said other one of said delaying means.

Claim 5

The circuit of claim 1 further comprising second means, coupled to said delaying means and to said detecting means, for selectively coupling an input of a second one of said delaying means to an input of a second other one of said delaying means in response to said detecting of said magnitude transition.

Claim 6

The circuit of claim 1 wherein said detecting means includes means for developing a detection signal of predetermined duration responsive to detecting said magnitude transition, said detection signal determining the duration of said selective coupling.

Claim 7

The circuit of claim 1 wherein said detecting means includes comparison means for detecting a magnitude difference between non-consecutive ones of said successively delayed input signals which exceeds a predetermined value.

Claim 8

The circuit of claim 6 wherein said detecting means further includes second comparison means for detecting a magnitude difference between further ones of said successively delayed input signals which is less than a second predetermined value.

Claim 9

The circuit of claim 1 further comprising control means for developing an enabling signal, and means for applying said enabling signal to said detecting means to enable said detecting of a magnitude transition.

Claim 10

The circuit of claim 8 wherein said control means develops said enabling signal in response to a transition of a second input signal which is related in time to said input signals received at said input.

Claim 11

The circuit of claim 9 wherein said input signals are representative of chrominance components of television signals and wherein said second input signals are representative of luminance components thereof.

Claim 12

A signal processing circuit comprising: first and second delaying means, having respective inputs and outputs, for respectively delaying signals applied to said inputs; multiplexing means, having a first input to which the output of said first delaying means is coupled, having a second input and having an output coupled to the input of said second delaying means, said multiplexing means for selectively coupling its first and second inputs to its output in response to a control signal; means for applying the same input signals to the input of said first delaying means and to the second input of said multiplexing means; detecting means for developing said control signal in response to a predetermined magnitude transition condition of said input signals and for applying said control signal to said multiplexing means to selectively interconnect the inputs of said first and second delay means.

Claim 13

A signal processing circuit comprising: first and second delaying means, having respective inputs and outputs, for respectively delaying signals applied to said inputs; multiplexing means, having a first input to which the output of said first delaying means is coupled, having a second input and having an output coupled to the input of said second delaying means, said multiplexing means for selectively coupling its first and second inputs to its output in response to a control signal; means for applying the same input signals to the input of said first delaying means and to the second input of said multiplexing means; detecting means for developing said control signal in response to a predetermined magnitude transition condition of said input signals and for applying said control signal to said multiplexing means to selectively interconnect the inputs of said first and second delay means.

Claim 14

The circuit of claim 11 wherein said detecting means comprises a comparing means for developing said control signal in response to the magnitude of said input signals changing in excess of a predetermined amount.

Claim 15

The circuit of claim 11 further comprising: third delaying means, having an input and an output, for delaying signals applied to its input; second multiplexing means, having a first input to which the output of said second delaying means is coupled, having a second input to which the output of said third delaying means is coupled, and having an output coupled to the input of said third delaying means, said multiplexing means for selectively coupling its first and second inputs to its output in response to said control signal.

Claim 16

The circuit of claim 13 wherein said detecting means comprises comparing means having a first input to which the input of one of said first, second and third delaying means is coupled, having a second input to which the output of one of said first, second and third delaying means is coupled, and having an output, for developing said control signal at its output in response to the magnitudes of signals at its first and second inputs differing by said predetermined amount.

Claim 17

The circuit of claim 11 further comprising: control means for developing an enabling signal, and means for applying said enabling signal to said detecting means to enable said detecting of a magnitude transition, wherein said control means develops said enabling signal in response to a transition of a second input signal which is related in time to said input signals received at said input.

Claim 18

A signal processing circuit comprising: an input for receiving input signals, and an output at which output signals responsive to said input signals are produced;

Claim 19

A signal processing circuit comprising: an input for receiving input signals, and an output at which output signals responsive to said input signals are produced;

Claim 20

a plurality N of delaying means coupled in cascade between said input and said output for successively delaying samples of said input signals, wherein N is an integer; first multiplexing means, interposed in said cascade coupling of said delaying means, having an output coupled to an input of a Jth one of said delaying means, and having first and second inputs respectively coupled to the outputs of a (J-1)th and a (J-R)th ones of said delaying means, where J is an integer no greater than N and R is a positive integer greater than 1 but less than (J-1), said first multiplexing means for selectively coupling its first and second inputs to its output in response to a control signal; second multiplexing means, interposed in said cascade coupling of said delaying means, having an output coupled to the input of a Kth one of said delaying means, and having first and second inputs respectively coupled to the outputs of a (K-1)th and a (K+S)th ones of said delaying means, where K is an integer no greater than N and S is a positive integer less than (N-K+1), said second multiplexing means for selectively coupling its first and second inputs to its output in response to said control signal; first detecting means, coupled to said delaying means and responsive to a first group of at least two consecutive input signal samples, for detecting that the magnitudes of said first group of consecutive input signal samples are within a predetermined range of relative magnitudes; second detecting means, coupled to said delaying means and responsive to a second group of at least two other consecutive input signal samples, for detecting that the magnitudes of said second group of consecutive input samples are within a predetermined range of relative magnitudes; third detecting means, coupled to said delaying means and responsive to two non-consecutive input signal samples, for detecting that the magnitudes of said two non-consecutive input signal samples differ by at least a predetermined amount; and means for developing said control signal in response to said detecting by said first, second and third detecting means and for applying said control signal to said first and second multiplexing means.

Claim 21

a plurality N of delaying means coupled in cascade between said input and said output for successively delaying samples of said input signals, wherein N is an integer; first multiplexing means, interposed in said cascade coupling of said delaying means, having an output coupled to an input of a Jth one of said delaying means, and having first and second inputs respectively coupled to the outputs of a (J-1)th and a (J-R)th ones of said delaying means, where J is an integer no greater than N and R is a positive integer greater than 1 but less than (J-1), said first multiplexing means for selectively coupling its first and second inputs to its output in response to a control signal; second multiplexing means, interposed in said cascade coupling of said delaying means, having an output coupled to the input of a Kth one of said delaying means, and having first and second inputs respectively coupled to the outputs of a (K-1)th and a (K+S)th ones of said delaying means, where K is an integer no greater than N and S is a positive integer less than (N-K+1), said second multiplexing means for selectively coupling its first and second inputs to its output in response to said control signal; first detecting means, coupled to said delaying means and responsive to a first group of at least two consecutive input signal samples, for detecting that the magnitudes of said first group of consecutive input signal samples are within a predetermined range of relative magnitudes; second detecting means, coupled to said delaying means and responsive to a second group of at least two other consecutive input signal samples, for detecting that the magnitudes of said second group of consecutive input samples are within a predetermined range of relative magnitudes; third detecting means, coupled to said delaying means and responsive to two non-consecutive input signal samples, for detecting that the magnitudes of said two non-consecutive input signal samples differ by at least a predetermined amount; and means for developing said control signal in response to said detecting by said first, second and third detecting means and for applying said control signal to said first and second multiplexing means.

Claim 22

The circuit of claim 16 wherein said two non-consecutive samples include one sample from each of said first and second groups of consecutive samples.

Claim 23

The circuit of claim 16 further comprising control means for developing an enabling signal, and means for applying said enabling signal to said means for developing to enable said developing of said control signal.

Claim 24

The circuit of claim 18 wherein said control means develops said enabling signal in response to a transition of a second input signal which is related in time to said input signals received at said input.

Claim 25

The circuit of claim 19 wherein said input signals are representative of chrominance components of television signals and wherein said second input signals are representative of luminance components thereof.