US4551822A
Expired / Lapsed
US
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Dynamic semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1982-12-07
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Granted: 1985-11-05
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Expires: 2002-12-07
Abstract
Abstract A dynamic semiconductor memory device having a refresh-address generator, includes an initial resetting circuit for resetting the output signals of a refresh-address counter when the power supply is turned on, thereby eliminating the need for counter checking procedures prior to the examination of the refresh-address generator.
Inventors
- 👤 Yoshihiro Takemae
- 👤 Katsuhiko Kabashima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 05:18
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C29/00; G11C29/02
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
212 words
A dynamic semiconductor memory device capable of performing a cyclic refresh operation in response to an external control signal indicative of a state of the refresh operation, comprising: memory cells, each having a capacitor for storing data; a refresh-control clock generator for generating a clock signal in response to the external control signal; a refresh-address counter, operatively connected to said refresh-control clock generator, for sequentially generating refresh-address signals in response to said clock signal, said memory cells being refreshed when addressed by said refresh-address signals, respectively, said refresh-address counter being capable of sequentially changing said refresh-address signals in response to said clock signal and retaining the last one of said refresh-address signals in the absence of said clock signal, and said refresh-address counter being capable of resuming the sequential change of said refresh-address signals starting with said retained last one of said refresh-address signals in response to said clock signal; an initial resetting means, operatively connected to said refresh-address counter, for resetting said refresh-address counter so as to set predetermined initial refresh-address signals in said refresh-address counter; and a power supply line, operatively connected to said initial resetting means, for supplying power to at least said initial resetting means, said initial resetting means resetting said refresh-address counter when power is turned on.
Claim 2
Dependent Claim
212 words
A dynamic semiconductor memory device capable of performing a cyclic refresh operation in response to an external control signal indicative of a state of the refresh operation, comprising: memory cells, each having a capacitor for storing data; a refresh-control clock generator for generating a clock signal in response to the external control signal; a refresh-address counter, operatively connected to said refresh-control clock generator, for sequentially generating refresh-address signals in response to said clock signal, said memory cells being refreshed when addressed by said refresh-address signals, respectively, said refresh-address counter being capable of sequentially changing said refresh-address signals in response to said clock signal and retaining the last one of said refresh-address signals in the absence of said clock signal, and said refresh-address counter being capable of resuming the sequential change of said refresh-address signals starting with said retained last one of said refresh-address signals in response to said clock signal; an initial resetting means, operatively connected to said refresh-address counter, for resetting said refresh-address counter so as to set predetermined initial refresh-address signals in said refresh-address counter; and a power supply line, operatively connected to said initial resetting means, for supplying power to at least said initial resetting means, said initial resetting means resetting said refresh-address counter when power is turned on.
Claim 3
Dependent Claim
118 words
A dynamic semiconductor memory device as set forth in claim 1, wherein said refresh-address counter has an output end, further comprising an internal oscillation circuit operatively connected to said power supply line and said initial resetting means, and having an oscillating output end for providing an oscillating signal, wherein said initial resetting means comprises pumping circuits each having two input ends connected to said oscillating output ends and two output ends, connected to the output end of said refresh-address counter, and wherein each of said pumping circuits comprises means for providing different rising times of the voltages at said two output ends in response to an increase in amplitude of the oscillating signal after power is turned on.
Claim 4
Dependent Claim
76 words
A dynamic semiconductor memory device as set forth in claim 2, wherein said refresh-address counter further comprises flip-flops, respectively, operatively connected to said pumping circuits, each having a non-inverted output end and an inverted output end, a first of said two output ends of each of said pumping circuits being connected to said non-inverted output end, a second of said two output ends of each of said pumping cicruits being connected to said inverted output end.
Claim 5
Dependent Claim
198 words
A dynamic semiconductor memory device as set forth in claim 3, wherein each of said pumping circuits comprises a first pumping circuit and a second pumping circuit, said first pumping circuit comprising: a first MOS transistor having a gate and a source; a second MOS transistor having a gate operatively connected to the source of said first MOS transistor and to said oscillating output end of said internal oscillation circuit, and having a source operatively connected to the gate of said first MOS transistor and to said non-inverted output and inverted output ends of each of said flip-flops; a first capacitor operatively connected in series between said power supply line and ground, said second pumping circuit comprising: a third MOS transistor having a gate and a source; a fourth MOS transistor having a gate operatively connected to the source of said third MOS transistor and to said oscillating output end of said internal oscillation circuit, and having a source operatively connected to the gate of said third MOS transistor and to said non-inverted output and inverted output ends of each of said flip-flops; and a second capacitor operatively connected in series between said power supply line and ground.
Claim 6
Dependent Claim
27 words
A dynamic semiconductor memory device as set forth in claim 4, wherein the capacitance of said first capacitor is different from the capacitance of said second capacitor.
Claim 7
Dependent Claim
30 words
A dynamic semiconductor memory device as set forth in claim 5, wherein each of said flip-flops comprises two transistors cross-coupled to each other, said two transistors having different mutual conductances.
Claim 8
Dependent Claim
97 words
A refresh-address counter for a dynamic semiconductor memory device operatively connected to a power supply, comprising: a flip-flop having an input terminal and an inverted output terminal and a non-inverted output terminal; a first transistor operatively connected between the input terminal of said flip-flop and the power supply; a plurality of second transistors operatively connected in parallel between the input terminal of said flip-flop and ground; and a pumping circuit operatively connected to said flip-flop, comprising: a first pumping unit operatively connected to said flip-flop; and a second pumping unit operatively connected to said first pumping unit.
Claim 9
Dependent Claim
97 words
A refresh-address counter for a dynamic semiconductor memory device operatively connected to a power supply, comprising: a flip-flop having an input terminal and an inverted output terminal and a non-inverted output terminal; a first transistor operatively connected between the input terminal of said flip-flop and the power supply; a plurality of second transistors operatively connected in parallel between the input terminal of said flip-flop and ground; and a pumping circuit operatively connected to said flip-flop, comprising: a first pumping unit operatively connected to said flip-flop; and a second pumping unit operatively connected to said first pumping unit.
Claim 10
Dependent Claim
179 words
A dynamic semiconductor memory device as set forth in claim 7, operatively connected to receive an oscillating signal, wherein said first pumping unit comprises: a second transistor having a gate operatively connected to receive the oscillating signal and having a drain and a source; a third transistor having a source commonly connected to the gate and the drain of said second transistor and having a gate operatively connected to the source of said second transistor and to the non-inverted output terminal of said flip-flop; a first capacitor operatively connected between the source of said second transistor and ground; wherein said second pumping unit comprises: a fourth transistor having a gate operatively connected to receive the oscillating signal and having a drain and a source; a fifth transistor having a source commonly connected to the gate and the drain of said fourth transistor and having a gate commonly connected to the source of said fourth transistor and to the inverted output terminal of said flip-flop; and a second capacitor operatively connected between the source of said fourth transistor and ground.
References Cited (Backward Citations)
US3737879A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-11-04 | 1989-05-06 | 1989-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-11-04 | 1993-05-06 | 1993-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-11-04 | 1997-05-06 | 1997-11-05 | $7700.00 | Window Closed / Lapsed |