Patent US4551705A successfully refreshed from Google Patents.
US4551705A
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Programmable integrated circuit AC resistor network
Assignee: Hughes Training Inc
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Filing: 1983-01-21
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Granted: 1985-11-05
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Expires: 2003-01-21
Abstract
Abstract A monolithic integrated circuit D-to-A converter and programmable AC resistor network and current source is disclosed in which an array of FET cells formed on a semiconductor body is divided into a plurality of distinct sets which may be grouped in two groups of corresponding sets. The source and drain regions respectively of all of the cells in each group are connected in common. The gate regions of the cells in each distinct set are also connected. In embodiments comprising two groups of cells, gate control logic is included which may supply signals of opposite binary states respectively to the gate regions of corresponding sets of cells in the two groups.
Inventors
- 👤 Robert D. Anderson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:14
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/74
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
356 words
A digitally programmable AC resistor network comprising: a monolithic body of semiconductor material having a plurality of ideally identical field effect transistor cells formed thereon, said cells being subject to unavoidable minor variations in characteristics, each field effect transistor cell having source, drain and gate regions, the electrical resistance between the source and drain regions varying with the voltage applied to the gate region, minimum source-drain resistance occurring in respnse to a gate voltage at least as great as a saturation value; a first conductor connecting the source regions of at least a first group of said cells to a first output terminal; a second conductor connecting the drain regions of the first group of said cells to a second output terminal; a third conductor connecting the drain regions of a second group of said cells to a third output terminal, the source regions of the second group of said cells being connected to said second output terminal; a plurality of control terminals; control conductor means individually connecting each control terminal to the gate regions of a distinct set of cells in said first group of cells so that the gate region of each cell in the first group of cells is connected to only one control terminal and each control terminal is connected to the gate regions of a predetermined plurality of cells, whereby variations of the characteristics of individual cells are averaged out to result in electrical resistance between the first and second output terminals which is inversely proportional to the number of cells in the sets of cells whose gate regions are supplied with voltages at least as great as the saturation value; and inverter means individually connecting each control terminal to the gate regions of a distinct set of cells in said second group of cells so that the gate region of each cell in said second group of cells is connected through an inverter to only one control terminal and each control terminal is connected through an inverter to the gate region of a predetermined plurality of cells, whereby the resistor network is operable as a digitally controlled variable voltage divider.
Claim 2
Dependent Claim
356 words
A digitally programmable AC resistor network comprising: a monolithic body of semiconductor material having a plurality of ideally identical field effect transistor cells formed thereon, said cells being subject to unavoidable minor variations in characteristics, each field effect transistor cell having source, drain and gate regions, the electrical resistance between the source and drain regions varying with the voltage applied to the gate region, minimum source-drain resistance occurring in respnse to a gate voltage at least as great as a saturation value; a first conductor connecting the source regions of at least a first group of said cells to a first output terminal; a second conductor connecting the drain regions of the first group of said cells to a second output terminal; a third conductor connecting the drain regions of a second group of said cells to a third output terminal, the source regions of the second group of said cells being connected to said second output terminal; a plurality of control terminals; control conductor means individually connecting each control terminal to the gate regions of a distinct set of cells in said first group of cells so that the gate region of each cell in the first group of cells is connected to only one control terminal and each control terminal is connected to the gate regions of a predetermined plurality of cells, whereby variations of the characteristics of individual cells are averaged out to result in electrical resistance between the first and second output terminals which is inversely proportional to the number of cells in the sets of cells whose gate regions are supplied with voltages at least as great as the saturation value; and inverter means individually connecting each control terminal to the gate regions of a distinct set of cells in said second group of cells so that the gate region of each cell in said second group of cells is connected through an inverter to only one control terminal and each control terminal is connected through an inverter to the gate region of a predetermined plurality of cells, whereby the resistor network is operable as a digitally controlled variable voltage divider.
Claim 3
Dependent Claim
28 words
The resistor network of claim 1 wherein the distinct sets of field effect transistor cells in the first and second groups of cells comprise different numbers of cells.
Claim 4
Dependent Claim
48 words
The resistor network of claim 2 wherein the number of cells in each set of cells in each of the first and second groups of cells is related to the number of cells in each of the other sets in the same group by a factor of two.
Claim 5
Dependent Claim
13 words
A digitally programmable AC resistor network having at least three output terminals comprising:
Claim 6
Dependent Claim
13 words
A digitally programmable AC resistor network having at least three output terminals comprising:
Claim 7
Dependent Claim
282 words
a monolithic semiconductor body having first and second groups of ideally identical field effect transistor cells formed thereon, each cell having source, drain and gate regions, each cell further providing maximum electrical resistance between its source and drain regions in response to a binary gate signal of a first state and providing minimum electrical resistance between its source and drain regions in response to a binary gate signaI of a second state, the first and second groups of cells each being subdivided into separate sets of cells, each set containing a plurality of cells; first, second and third output terminals on said semiconductor body; a first conductor connecting the source regions of the cells in said first group to said first output terminal; a second conductor connecting the drain regions of the cells in said first group and the source regions of the cells in said second group to said second output terminal; a third conductor connecting the drain regions of the cells in said second group to said third output terminal; control terminal means on said semiconductor body; and gate signal means connecting said control terminal means to the gate regions of the cells for selectively supplying binary control signals to the gate regions of corresponding sets of cells in said first and second groups, said gate signal means operating so that when a binary gate signal of one of the first and second states is supplied to the gate regions of a selected set of cells in said first group, a binary gate signal of the other of the first and second states is concurrently supplied to the gate regions of the corresponding set of cells in said second group.
Claim 8
Dependent Claim
282 words
a monolithic semiconductor body having first and second groups of ideally identical field effect transistor cells formed thereon, each cell having source, drain and gate regions, each cell further providing maximum electrical resistance between its source and drain regions in response to a binary gate signal of a first state and providing minimum electrical resistance between its source and drain regions in response to a binary gate signaI of a second state, the first and second groups of cells each being subdivided into separate sets of cells, each set containing a plurality of cells; first, second and third output terminals on said semiconductor body; a first conductor connecting the source regions of the cells in said first group to said first output terminal; a second conductor connecting the drain regions of the cells in said first group and the source regions of the cells in said second group to said second output terminal; a third conductor connecting the drain regions of the cells in said second group to said third output terminal; control terminal means on said semiconductor body; and gate signal means connecting said control terminal means to the gate regions of the cells for selectively supplying binary control signals to the gate regions of corresponding sets of cells in said first and second groups, said gate signal means operating so that when a binary gate signal of one of the first and second states is supplied to the gate regions of a selected set of cells in said first group, a binary gate signal of the other of the first and second states is concurrently supplied to the gate regions of the corresponding set of cells in said second group.
Claim 9
Dependent Claim
103 words
The resistor network of claim 4 wherein said gate signal means comprises: conductors individually connecting control terminals in said control terminal means to distinct sets of cells in said first group so that the gate region of each cell is connected to only one control terminal and each control terminal is connected to the gate regions of only a predetermined set of cells; and inverter means including an inverter connecting each control terminal to only the gate regions of the set of cells in the second group corresponding to the set of cells in the first group connected to the same control terminal.
Claim 10
Dependent Claim
40 words
The resistor network of claim 5 wherein the distinct sets of field effect transistor cells in each group comprise different numbers of cells, and corresponding sets of cells in said first and second groups contain the same number of cells.
Claim 11
Dependent Claim
39 words
The resistor network of claim 6 wherein the number of cells in each set in a group is related to the number of cells in each of the other sets in the same group by a factor of two.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-11-04 | 1989-05-06 | 1989-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-11-04 | 1993-05-06 | 1993-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-11-04 | 1997-05-06 | 1997-11-05 | $7700.00 | Window Closed / Lapsed |