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US4550423A
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Stereo MPX circuit
Assignee: Trio KK
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Filing: 1984-02-03
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Granted: 1985-10-29
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Expires: 2004-02-03
Abstract
Abstract A stereo multiplex circuit which can reduce a distortion of an FM demodulated signal to be generated due to nonlinearity of the frequency vs. amplitude/phase characteristics of a band-pass filter at an intermediate frequency amplifier stage of an FM receiver. This circuit includes a circuit for multiplying signals consisting of right-channel and left-channel signals and for adjusting the level of this multiplication signal into a suitable magnitude and thereafter inserting into the right and left channels, thereby causing a harmonic distortion to disappear.
Inventors
- 👤 Michinori Naito
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 11:16
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/06; H04B1/16; H04B1/1646; H04B1/1661; H04B1/1669; H04B1/1676
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
133 words
In combination, a stereo multiplex circuit for outputting right-channel and left-channel signals by decoding a stereo composite signal; a circuit for multiplying signals consisting of said right-channel and left-channel signals; a circuit for receiving an output signal of said multiplier and for adjusting the level of the magnitude, thereby to output; and a circuit for inserting an output signal of said level control circuit into the right and left channels to compensate high-order harmonic distortion in the right and left channels, wherein a level ratio of input/output of said level control circuit is set to a value so as to minimize the high-order harmonic distortion in the right and left channels existing prior to insertion of the output of said level control circuit into the right and left channels by said inserting circuit.
Claim 2
Dependent Claim
133 words
In combination, a stereo multiplex circuit for outputting right-channel and left-channel signals by decoding a stereo composite signal; a circuit for multiplying signals consisting of said right-channel and left-channel signals; a circuit for receiving an output signal of said multiplier and for adjusting the level of the magnitude, thereby to output; and a circuit for inserting an output signal of said level control circuit into the right and left channels to compensate high-order harmonic distortion in the right and left channels, wherein a level ratio of input/output of said level control circuit is set to a value so as to minimize the high-order harmonic distortion in the right and left channels existing prior to insertion of the output of said level control circuit into the right and left channels by said inserting circuit.
Claim 3
Dependent Claim
51 words
A stereo multiplex circuit in accordance with claim 1, wherein said multiplier multiplies a sum signal and a differential signal of the right-channel and left-channel signals, and wherein said level control circuit is set to a level ratio such as to extinguish the second harmonic distortion existing in said differential signal.
Claim 4
Dependent Claim
46 words
A stereo multiplex circuit in accordance with claim 1, wherein said multiplier cubes a differential signal of the right-channel and left-channel signals, and wherein said level control is set to a level ratio such as to extinguish the third harmonic distortion existing in said differential signal.
References Cited (Backward Citations)
US4356350A
Cited
US4502148A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-10-28 | 1989-04-29 | 1989-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-10-28 | 1993-04-29 | 1993-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-10-28 | 1997-04-29 | 1997-10-29 | $7700.00 | Window Closed / Lapsed |