US4550390A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: NEC Corp
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Filing: 1982-04-07
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Granted: 1985-10-29
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Expires: 2002-04-07
Abstract
Abstract A semiconductor memory having a construction making it less susceptible to α-rays. The memory includes a pair of transistors connected in a flip-flop arrangement. In each memory transistor there is a buried region of high concentration which contacts the collector region of the same impurity. The base region consists of a relatively low concentration part, in which the emitter or emitters are formed, and a high concentration part, to which the base electrode is attached. The high concentration part of the base region extends down to and protrudes into the high concentration buried region, resulting in a higher than usual collector-base capacitance. The latter causes the voltage change due to α-rays to be less than it otherwise would be.
Inventors
- 👤 Tsutomu Akashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:57
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4116; H; H10; H10B; H10B10/00; H10B10/10; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10W; H10W42/00; H10W42/20; H10W42/25
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
162 words
A semiconductor memory device comprising a semiconductor substrate of one conductivity type, a semiconductor epitaxial layer of the opposite conductivity type provided on said semiconductor substrate, a first layer of said opposite conductivity type buried between said semiconductor substrate and said semiconductor epitaxial layer and having a higher impurity concentration than said semiconductor epitaxial layer, a first base region of said one conductivity type provided along a major surface of said semiconductor epitaxial layer, the bottom face of said first base region being separated from said first layer, a second base region of said one conductivity type formed in said semiconductor epitaxial layer so as to extend from the surface thereof down to said first layer and to contact with said first base region, said second base region having a higher impurity concentration than said first base region, an emitter region of said opposite conductivity type formed in said first base region, and a base electrode connected to said second base region.
Claim 2
Dependent Claim
162 words
A semiconductor memory device comprising a semiconductor substrate of one conductivity type, a semiconductor epitaxial layer of the opposite conductivity type provided on said semiconductor substrate, a first layer of said opposite conductivity type buried between said semiconductor substrate and said semiconductor epitaxial layer and having a higher impurity concentration than said semiconductor epitaxial layer, a first base region of said one conductivity type provided along a major surface of said semiconductor epitaxial layer, the bottom face of said first base region being separated from said first layer, a second base region of said one conductivity type formed in said semiconductor epitaxial layer so as to extend from the surface thereof down to said first layer and to contact with said first base region, said second base region having a higher impurity concentration than said first base region, an emitter region of said opposite conductivity type formed in said first base region, and a base electrode connected to said second base region.
Claim 3
Dependent Claim
25 words
A semiconductor memory device as claimed in claim 1, in which said second base region protrudes into said first layer by 0.1 to 0.4 μm.
Claim 4
Dependent Claim
40 words
A semiconductor memory device as claimed in claim 1, in which the bottom of said second base region makes contact with a part of said first layer having an impurity concentration of 1×10 17 to 5×10 18 /cm 3 .
Claim 5
Dependent Claim
144 words
A semiconductor memory device comprising a semiconductor body of one conductivity type, a semiconductor layer of the opposite conductivity type provided on said semiconductor body, a buried layer of said opposite conductivity type formed between said semiconductivity body and said semiconductor layer and having a higher impurity concentration than said semiconductor layer, a base region of said one conductivity type provided along a major surface of said semiconductor layer, said base region including a center portion and first and second side portions abutting against said center portion and having a lower impurity concentration than that of said center portion, said center portion being extended from said major surface of said semiconductor layer into said buried layer, said first and second side portions being separated from said buried layer, and a base electrode connected to the surface of said center portion of said base region.
Claim 6
Dependent Claim
144 words
A semiconductor memory device comprising a semiconductor body of one conductivity type, a semiconductor layer of the opposite conductivity type provided on said semiconductor body, a buried layer of said opposite conductivity type formed between said semiconductivity body and said semiconductor layer and having a higher impurity concentration than said semiconductor layer, a base region of said one conductivity type provided along a major surface of said semiconductor layer, said base region including a center portion and first and second side portions abutting against said center portion and having a lower impurity concentration than that of said center portion, said center portion being extended from said major surface of said semiconductor layer into said buried layer, said first and second side portions being separated from said buried layer, and a base electrode connected to the surface of said center portion of said base region.
Claim 7
Dependent Claim
28 words
A semiconductor memory device as claimed in claim 4, in which said center portion of said base region protrudes into said buried layer by 0.1 to 0.4 μm.
Claim 8
Dependent Claim
43 words
A semiconductor memory device as claimed in claim 4, in which the bottom of said center portion of said base region makes contact with a part of said buried layer having an impurity concentration of 1×10 17 to 5×10 18 /cm 3 .
Claim 9
Dependent Claim
34 words
A semiconductor memory device as claimed in claim 4, further comprising first and second emitter regions of said opposite conductivity type provided within said first and second side portions of said base region, respectively.
Claim 10
Dependent Claim
25 words
A semiconductor memory device as claimed in claim 4, further comprising a base electrode of silicon connected to said center portion of said base region.
References Cited (Backward Citations)
US4366554A
Cited
US4419745A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-10-28 | 1989-04-29 | 1989-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-10-28 | 1993-04-29 | 1993-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-10-28 | 1997-04-29 | 1997-10-29 | $7700.00 | Window Closed / Lapsed |