US4419745A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1980-08-20
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Granted: 1983-12-06
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Expires: 2000-08-20
Abstract
Abstract An improvement of a semiconductor integrated circuit device of a memory cell array which is formed by integrated injection logic memory cells. The semiconductor integrated circuit includes integration injection logic memory cells which are arranged in matrix form, word lines and bit lines which are connected to the memory cells arranged in the row or column directions and which are formed by a semiconductor bulk. A current source is provided around the middle portion of each word line.
Inventors
- 👤 Kazuhiro Toyoda
- 👤 Chikai Ono
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:01
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; G11C5/00; G11C5/06; G11C5/063; H; H10; H10B; H10B10/00; H10B10/10
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
140 words
A semiconductor memory device having a plurality of word lines formed on a semiconductor substrate, and a plurality of integrated-injection-logic memory cells commonly connected to each of said word lines, said memory cells being arranged in a matrix form, said semiconductor memory device comprising current sources, respectively connected to said word lines, only a single one of said current sources connected around the middle portion of a corresponding one of said plurality of word lines , a bias circuit for providing a bias voltage to all of said current sources, and only a single pair of bias lines operatively connected between said bias circuit and all of said current sources, said single pair of bias lines extending across the middle portion of each of said plurality of word lines and being orthogonal to each of said plurality of word lines.
Claim 2
Dependent Claim
140 words
A semiconductor memory device having a plurality of word lines formed on a semiconductor substrate, and a plurality of integrated-injection-logic memory cells commonly connected to each of said word lines, said memory cells being arranged in a matrix form, said semiconductor memory device comprising current sources, respectively connected to said word lines, only a single one of said current sources connected around the middle portion of a corresponding one of said plurality of word lines , a bias circuit for providing a bias voltage to all of said current sources, and only a single pair of bias lines operatively connected between said bias circuit and all of said current sources, said single pair of bias lines extending across the middle portion of each of said plurality of word lines and being orthogonal to each of said plurality of word lines.
Claim 3
Dependent Claim
25 words
A semiconductor memory device as claimed in claim 1, further comprising a plurality of bit lines (B.sub..0. and B 1 ) intersecting said word lines.
Claim 4
Dependent Claim
64 words
A semiconductor memory device as claimed in claim 2, further comprising a bit driver for driving said bit lines, said bias circuit being provided at the middle portion of said bit driver, each single one of said current sources being connected to said bias circuit through said pair of bias lines (l 5 , l 6 ) extending in parallel to said bit lines.
Claim 5
Dependent Claim
48 words
A semiconductor memory device as claimed in claim 3, wherein each said single current source is comprised of a transistor, the base of the transistor being connected to one of said bias lines and the emitter of said transistor being connected to the other of said bias lines.
Claim 6
Dependent Claim
130 words
A semiconductor memory device comprising: a semiconductor substrate; a plurality of word lines formed on said semiconductor substrate; a plurality of injection-logic memory cells formed in said semiconductor substrate in a matrix form and commonly connected to each of said plurality of word lines; current sources, respectively connected to said plurality of word lines, only a single one of said current sources operatively connected at approximately the middle of a corresponding one of said plurality of word lines; a bias circuit for providing a bias voltage to said current sources; and only a single pair of bias lines, operatively connected between said bias circuit and said current sources, extending across the middle of each of said plurality of word lines and orthogonal to each of said plurality of word lines.
Claim 7
Dependent Claim
130 words
A semiconductor memory device comprising: a semiconductor substrate; a plurality of word lines formed on said semiconductor substrate; a plurality of injection-logic memory cells formed in said semiconductor substrate in a matrix form and commonly connected to each of said plurality of word lines; current sources, respectively connected to said plurality of word lines, only a single one of said current sources operatively connected at approximately the middle of a corresponding one of said plurality of word lines; a bias circuit for providing a bias voltage to said current sources; and only a single pair of bias lines, operatively connected between said bias circuit and said current sources, extending across the middle of each of said plurality of word lines and orthogonal to each of said plurality of word lines.
Claim 8
Dependent Claim
79 words
A semiconductor memory device as claimed in claim 5, further comprising: a plurality of bit lines intersecting said word lines; a bit driver, operatively connected to said plurality of bit lines, for driving said plurality of bit lines; and said bias circuit operatively connected to the middle portion of said bit driver, each of said current sources being connected to said bias circuit through said single pair of bias lines which extend parallel to said plurality of bit lines.
Claim 9
Dependent Claim
52 words
A semiconductor memory device as claimed in claim 6, wherein each of said current sources comprises a transistor having a base operatively connected to one bias line of said single pair of bias lines and having an emitter operatively connected to the other bias line of said single pair of bias lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-05 | 1987-06-06 | 1987-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-05 | 1991-06-06 | 1991-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-05 | 1995-06-06 | 1995-12-06 | $7700.00 | Window Closed / Lapsed |