US4547868A
Expired / Lapsed
US
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Dummy-cell circuitry for dynamic read/write memory
Assignee: Texas Instruments Inc
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Filing: 1984-07-26
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Granted: 1985-10-15
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Expires: 2004-07-26
Abstract
Abstract A semiconductor dynamic read/write memory circuit using one-transistor storage cells and balanced bit lines with differential sense amplifiers employs dummy capacitors which are the same size as the storage capacitors. The dummy cell produces a signal on the bit line half that of the storage cell due to a level-shift circuitry connected to the dummy cells. The dummy capacitor is precharged to a reference voltage, and at the beginning of an active cycle the dummy capacitor is charge-shared with another capacitance of the same size, to change the reference level. The net signal is thus equal to that of a capacitor one-half the size of the storage capacitors.
Inventors
- 👤 Jimmie D. Childers
- 👤 Adin E. Hyslop
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 15:28
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4099
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
156 words
A semiconductor memory device comprising: an array of rows and columns of storage cells, each storage cell having a storage capacitor, at least one row of dummy cells adjacent said array of storage cells, each dummy cell having a capacitor, and an access transistor connecting the dummy capacitor to a column line, addressing means for activating one of said rows of storage cells and activating said row of dummy cells at a first time in an operating cycle, precharge means coupled to said dummy capacitor at a time prior to said first time in and operating cycle, and decoupled from said dummy capacitor at said first time and for a period thereafter, to thereby precharge said dummy capacitor to a reference voltage, and a charge-sharing circuit including a second capacitor coupled to said dummy capacitor for a time period just before said first time in an operating cycle to change the charge in the dummy capacitor.
Claim 2
Dependent Claim
156 words
A semiconductor memory device comprising: an array of rows and columns of storage cells, each storage cell having a storage capacitor, at least one row of dummy cells adjacent said array of storage cells, each dummy cell having a capacitor, and an access transistor connecting the dummy capacitor to a column line, addressing means for activating one of said rows of storage cells and activating said row of dummy cells at a first time in an operating cycle, precharge means coupled to said dummy capacitor at a time prior to said first time in and operating cycle, and decoupled from said dummy capacitor at said first time and for a period thereafter, to thereby precharge said dummy capacitor to a reference voltage, and a charge-sharing circuit including a second capacitor coupled to said dummy capacitor for a time period just before said first time in an operating cycle to change the charge in the dummy capacitor.
Claim 3
Dependent Claim
30 words
A device according to claim 1 wherein said charge-sharing means discharges said second capacitor to ground and charges said dummy capacitor to a positive voltage, prior to said time period.
Claim 4
Dependent Claim
15 words
A device according to claim 1 wherein said storage cells are one-transistor dynamic memory cells.
Claim 5
Dependent Claim
19 words
A device according to claim 1 wherein said dummy capacitor and said storage capacitor are of the same size.
Claim 6
Dependent Claim
112 words
A dummy cell circuit for coupling to a bit line of a dynamic read/write memory array, comprising: a dummy capacitor, an access transistor having a source-to-drain path and a gate, means connecting the source-to-drain path of the access transistor between said bit line and said dummy capacitor, means connected to said gate of said access transistor to activate said transistor at a given point in an operating cycle, and charge-sharing means, including a second capacitor connected to said dummy capacitor, and means to discharge the dummy second capacitor to ground and charge the dummy capacitor to a selected voltage level at a time prior to said given point in an operating cycle.
Claim 7
Dependent Claim
112 words
A dummy cell circuit for coupling to a bit line of a dynamic read/write memory array, comprising: a dummy capacitor, an access transistor having a source-to-drain path and a gate, means connecting the source-to-drain path of the access transistor between said bit line and said dummy capacitor, means connected to said gate of said access transistor to activate said transistor at a given point in an operating cycle, and charge-sharing means, including a second capacitor connected to said dummy capacitor, and means to discharge the dummy second capacitor to ground and charge the dummy capacitor to a selected voltage level at a time prior to said given point in an operating cycle.
Claim 8
Dependent Claim
22 words
A circuit according to claim 5 wherein said charge-sharing means includes a second transistor connecting said dummy capacitor to said second capacitor.
Claim 9
Dependent Claim
23 words
A circuit according to claim 6 wherein said means to precharge include third and fourth transistors each activated by precharge clock voltage means.
Claim 10
Dependent Claim
24 words
A circuit according to claim 5 wherein said memory array contains a plurality of one-transistor storage cells having storage capacitors of a given size.
Claim 11
Dependent Claim
27 words
A circuit according to claim 8 wherein said dummy capacitor and said second capacitor are each of about the same size as one of said storage capacitors.
Claim 12
Dependent Claim
28 words
A circuit according to claim 9 wherein said bit line is precharged to said voltage level at a time prior to said given point in an operating cycle.
Claim 13
Dependent Claim
22 words
A circuit according to claim 8 wherein said second capacitor is shared for a plurality of said dummy cells in said array.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-10-14 | 1989-04-15 | 1989-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-10-14 | 1993-04-15 | 1993-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-10-14 | 1997-04-15 | 1997-10-15 | $7700.00 | Window Closed / Lapsed |