Correlation detecting device

Claim 2

An image signal processing device used in an image correlation detecting device comprising: first and second analog shift registers for respectively retaining and shifting signals as an image of an object, said first and second analog shift registers forming respectively closed loops to shift signals in successive cycles, the signals in the bits in the first analog shift register and that in the second analog shift register being arranged to be offset relative to each other; comparison means for comparing said signals of the image for every corresponding bit of the first and second analog shift registers and producing a comparison value as an output; one of said shift registers including stepping means for shifting the signals in the bits said first and second analog shift registers relative to each other so as to vary the relationships between corresponding bits for every cycle of the analog shift registers; and adder means for adding outputs of said comparison means, said adder means making the addition for every 1 loop of the analog shift registers and producing a result of said addition as a correlation signal.

Claim 3

An image signal processing device according to claim 1, in which said step means makes the number of stages of analog shift registers in the first loop different from the other loop.

Claim 4

An image signal processing device according to claim 2, in which the comparison means contains a difference detection circuit to detect a difference between the corresponding bits.

Claim 5

An image signal processing device according to claim 3, in which the adder means contains an analog register or analog registers.

Claim 6

An image signal processing device according to claim 4, in which the analog shift registers are made of CCD's.

Claim 7

A correlation detecting device for detecting a correlation of an image, comprising: first and second signal receiving means to receive image signals; first and second analog shift registers to respectively retain and shift image signals received by said first and second signal receiving means, said analog shift registers respectively forming closed loops to shift signals in successive cycles, the bits in the first analog shift register and that in the second analog shift register being offset relative to each other; comparison means for comparing image signals retained by the analog shift registers for every corresponding bit of said registers and producing a comparison value as an output; one of said register including step means for shifting the signals in the bits of the shift registers relative to each other, said step means functioning every time the comparison means compares one cycle in the loop of the shift registers; adder means for adding output of the comparison means, wherein the addition by said adder means is made for each loop of the shift registers; and minimum value detecting means for detecting the minimum value of the adder means.

Claim 8

A correlation detecting device for detecting a correlation of an image, comprising: first and second signal receiving means to receive image signals; first and second analog shift registers to respectively retain and shift image signals received by said first and second signal receiving means, said analog shift registers respectively forming closed loops to shift signals in successive cycles, the bits in the first analog shift register and that in the second analog shift register being offset relative to each other; comparison means for comparing image signals retained by the analog shift registers for every corresponding bit of said registers and producing a comparison value as an output; one of said register including step means for shifting the signals in the bits of the shift registers relative to each other, said step means functioning every time the comparison means compares one cycle in the loop of the shift registers; adder means for adding output of the comparison means, wherein the addition by said adder means is made for each loop of the shift registers; and minimum value detecting means for detecting the minimum value of the adder means.

Claim 9

A device according to claim 6, in which the operating means contains shifting means for shifting relationships between the above-mentioned corresponding bits.

Claim 10

A device according to claim 7, in which the comparison means contains a difference detection circuit arranged to detect a difference between the corresponding bits.

Claim 11

A device according to claim 7, in which the comparison means contains a differential circuit arranged to detect a difference between the corresponding bits.

Claim 12

A device according to claim 8 or claim 9, in which the adder means contains an analog register or registers.

Claim 13

A device according to claim 10, in which the analog shift registers are made of CCD or CCD's.

Claim 14

A device according to claim 11, in which one of the signal receiving means and the analog shift register which retains the image signals from said signal receiving means are made of one CCD.

Claim 15

A correlation detecting device for detecting a correlation of an image, comprising: a pair of signal receiving means to receive image signals; a first analog shift register with a plurality of bits to retain the image signals received by one of the pair of signal receiving means, said first analog shift register forming a closed loop and circulating the image signals within the closed loop while shifting said image signals between each bit; a second analog shift register with a plurality of bits arranged to retain the image signals received by the other one of the pair of signal receiving means, said second analog shift register forming a closed loop and circulating said image signals within the closed loop while shifting said image signals between bits, the bits in the second analog shift register being offset relative to the first analog shift register; difference detecting means for detecting in turn a difference of image signals between prescribed bits in the first and second analog shift registers; one of said shift registers having step means for shifting the bits of the shift registers relative to each other by one bit during each cycle of circulation within the loop of the first analog shift register; adder means for operating a sum of outputs of the difference detection means during one cycle of circulation within the first analog shift register and successively registering sums of addition; minimum value detection means for detecting the minimum value of outputs of the adder means; and correlation detecting means for detecting a correlation of the image signals based on the minimum value obtained from the minimum value detecting means and a register address of the adder means at which said minimum value has been registered.

Claim 16

A correlation detecting device for detecting a correlation of an image, comprising: a pair of signal receiving means to receive image signals; a first analog shift register with a plurality of bits to retain the image signals received by one of the pair of signal receiving means, said first analog shift register forming a closed loop and circulating the image signals within the closed loop while shifting said image signals between each bit; a second analog shift register with a plurality of bits arranged to retain the image signals received by the other one of the pair of signal receiving means, said second analog shift register forming a closed loop and circulating said image signals within the closed loop while shifting said image signals between bits, the bits in the second analog shift register being offset relative to the first analog shift register; difference detecting means for detecting in turn a difference of image signals between prescribed bits in the first and second analog shift registers; one of said shift registers having step means for shifting the bits of the shift registers relative to each other by one bit during each cycle of circulation within the loop of the first analog shift register; adder means for operating a sum of outputs of the difference detection means during one cycle of circulation within the first analog shift register and successively registering sums of addition; minimum value detection means for detecting the minimum value of outputs of the adder means; and correlation detecting means for detecting a correlation of the image signals based on the minimum value obtained from the minimum value detecting means and a register address of the adder means at which said minimum value has been registered.

Claim 17

A device according to claim 13, in which the correlation detecting means contains counter means for counting numbers of circulations of the image signals within the first analog shift register until the minimum value detection means detects the above-mentioned minimum value.

Claim 18

A device according to claim 14, in which the operating means is so made that corresponding relationship of the image signals is made to deviate one bit by one bit.

Claim 19

A device according to claim 15, in which the adder means contains an analog register or analog registers.

Claim 20

A device according to claim 16, in which the first and second analog shift registers are made of CCD's.

Claim 21

A device according to claim 17, in which the signal receiving means and the analog shift registers are integrally made of a CCD.