Voltage and temperature compensated FET ring oscillator

Claim 2

In an oscillator circuit having inverter and delay stages coupled between a reference node and a first power supply terminal wherein the voltage at the reference node affects, in direct proportion, the frequency of oscillation of the oscillator circuit, a voltage compensation circuit, comprising: a depletion transistor having a first current electrode coupled to a second power supply terminal, a control electrode coupled to the first power supply terminal, and a second current electrode coupled to the reference node.

Claim 3

The oscillator circuit of claim 1, wherein each delay stage has a control terminal for controlling the delay thereof, further comprising a first diode-connected transistor coupled between the reference node and the control terminals of the delay stages.

Claim 4

The oscillator circuit of claim 2 further comprising a second diode-connected transistor interposed between the first diode-connected transistor and the control terminals of the delay stages.

Claim 5

The oscillator circuit of claim 3 further comprising a load coupled between the control terminals of the delay stages and the first power supply terminal.

Claim 6

In an oscillator circuit comprising: an inverter having an input and an output; delay means coupled to the output of said inverter for delaying the output of said inverter under control of a control signal; and feedback means coupled between said delay means and said inverter, for coupling the delayed output from said delay means to the input of said inverter; a temperature compensation circuit comprising: a first transistor having a first current electrode and a control electrode coupled to a first reference terminal, and a second current electrode; a second transistor having a first current electrode and a control electrode coupled to the second current electrode of the first transistor, and a second current electrode for providing the control signal to the delay means; and a load coupled between the second current electrode of the second transistor and a second reference terminal.

Claim 7

In an oscillator circuit comprising: an inverter having an input and an output; delay means coupled to the output of said inverter for delaying the output of said inverter under control of a control signal; and feedback means coupled between said delay means and said inverter, for coupling the delayed output from said delay means to the input of said inverter; a temperature compensation circuit comprising: a first transistor having a first current electrode and a control electrode coupled to a first reference terminal, and a second current electrode; a second transistor having a first current electrode and a control electrode coupled to the second current electrode of the first transistor, and a second current electrode for providing the control signal to the delay means; and a load coupled between the second current electrode of the second transistor and a second reference terminal.

Claim 8

An oscillator circuit, comprising: inverter and delay stages wherein each delay stage comprises a control transistor having a first current electrode as an input of the delay stage, a second current electrode as an output of the delay stage, and a control electrode; and a capacitor having a first terminal coupled to the second current electrode of the control transistor, and a second terminal coupled to a first reference terminal; a first transistor having a first current electrode and a control electrode coupled to a second reference terminal, and a second current electrode coupled to the control electrode of the control transistor of at least one delay stage; and a load coupled between the second current electrode of the first transistor and the first reference terminal.

Claim 9

An oscillator circuit, comprising: inverter and delay stages wherein each delay stage comprises a control transistor having a first current electrode as an input of the delay stage, a second current electrode as an output of the delay stage, and a control electrode; and a capacitor having a first terminal coupled to the second current electrode of the control transistor, and a second terminal coupled to a first reference terminal; a first transistor having a first current electrode and a control electrode coupled to a second reference terminal, and a second current electrode coupled to the control electrode of the control transistor of at least one delay stage; and a load coupled between the second current electrode of the first transistor and the first reference terminal.