Parity checking arrangement

Claim 2

A transmission integrity arrangement for a two-way plural channel communication system comprising means for interfacing with said channels, first and second read-only memory (ROM) means for opposite transmission directions for storing a data word for each time slot in said system transmitted to and received from said interface means, said data word including a destination selection code for each channel, the sense of parity bits for the message traversing the channel, the parity of the subsequent ROM address value and the overall parity of the ROM data word; counter means for controlling the read-out of the words of data from said first and second ROM means in sequence; and parity checking means for data received from said interface means and parity generator means for data transmitted to said interface means for producing localized indications of parity failure.

Claim 3

The transmission integrity arrangement set forth in claim 1 in which said first and second memory means are programmed with a sequence of multibit words, each word containing at least the selection code of the channel being served, the sense of the parity bit of the message data traversing the channel being served, the parity of the subsequent address of said ROM and the parity of the overall ROM data word.

Claim 4

The transmission integrity arrangement set forth in claim 2 in which said first and second memory means are preprogrammed to include two complementary sequences of multibit words directing parities of reverse sense for alternating frames of data in a given transmission direction.

Claim 5

The transmission integrity arrangement set forth in claim 1 in which the parity sense of message data for one transmission direction is reflected in the message data next returned in the opposite transmission direction in alternate frames.

Claim 6

The transmission integrity arrangement set forth in claim 1 in which said counter means synchronizes message data flow in both directions of transmission.

Claim 7

The transmission integrity arrangement set forth in claim 1 in which said parity generating means and said parity checking means responsive to said counter means provide the parity sense for words of message data in each direction of transmission through each channel in accordance with the sequences programmed into said first and second memories.

Claim 8

The transmission integrity arrangement set forth in claim 1 in which said parity checking means and said parity generating means compare the message data parity with the sense of the parity bits programmed into the respective first and second memory means for agreement and generate an error signal in the event of nonagreement.

Claim 9

The transmission integrity arrangement set forth in claim 7 further comprising an error register responsive to an error signal from said parity checking means for initiating a fault isolating test on said communication system.

Claim 10

The transmission integrity arrangement set forth in claim 8 further comprising a loopback path insertible between oppositely directed transmission directions of the several two-way channels for bypassing signals originating at a near-end of said system around a far-end thereof for fault isolation testing.

Claim 11

The transmission integrity arrangement set forth in claim 8 further comprising loopback paths insertible alternatively into either terminus between oppositely directed transmission directions of the several two-way channels for bypassing signals originating at the terminus opposite to that in which a loopback path is inserted.

Claim 12

The transmission integrity arrangement set forth in claim 1 further comprising first and second means each associated with one of said ROMs for temporarily storing said data words so as to introduce a predetermined delay, and means for comparing said parity bit of said ROM address value received from said temporary storage means with the parity bit of a subsequent ROM address in order to determine whether said counter means is functioning correctly.

Claim 13

In a multiplexer for transferring a plurality of bidirectional signals between a plurality of parallel links, each including a plurality of time-divided channels, and a pair of bidirectional serial links having first and second preprogrammed memory means storing for opposite transmission directions a word of data for each channel in such system including a selection code and parity bits for parallel channel data, and the time-slot address and the parity of the overall data word; counter means for controlling the read-out of words of data from such first and second memory means in sequence; first and second parity control means for opposite transmission directions; parity checking means and parity generating means for opposite transmission directions: the method for maintaining continuous transmission integrity within said multiplexer comprising the steps of (a) reading a word under the control of said counter means in sequence from said first memory to direct said first parity control means to apply a predetermined parity alternating from word to word to a signal word originating in a serial link destined for a particular parallel channel; (b) repeating the parity of the last signal received in a particular parallel channel in the next signal originating in the particular parallel channel; (c) comparing the parity of each signal proceeding from a particular parallel channel to a particular time slot serial link with a word stored in sequence in said second memory, and (d) generating an error signal upon the failure of a comparison between a signal originating in a parallel channel and the time slot in the applicable link in said second memory.

Claim 14

In a multiplexer for transferring a plurality of bidirectional signals between a plurality of parallel links, each including a plurality of time-divided channels, and a pair of bidirectional serial links having first and second preprogrammed memory means storing for opposite transmission directions a word of data for each channel in such system including a selection code and parity bits for parallel channel data, and the time-slot address and the parity of the overall data word; counter means for controlling the read-out of words of data from such first and second memory means in sequence; first and second parity control means for opposite transmission directions; parity checking means and parity generating means for opposite transmission directions: the method for maintaining continuous transmission integrity within said multiplexer comprising the steps of (a) reading a word under the control of said counter means in sequence from said first memory to direct said first parity control means to apply a predetermined parity alternating from word to word to a signal word originating in a serial link destined for a particular parallel channel; (b) repeating the parity of the last signal received in a particular parallel channel in the next signal originating in the particular parallel channel; (c) comparing the parity of each signal proceeding from a particular parallel channel to a particular time slot serial link with a word stored in sequence in said second memory, and (d) generating an error signal upon the failure of a comparison between a signal originating in a parallel channel and the time slot in the applicable link in said second memory.

Claim 15

The method set forth in claim 12 further comprising the step of closing a signaling loop between opposite transmission directions in a particular parallel channel for isolating faults from other parallel channels.

Claim 16

The method set forth in claim 12 further comprising the steps of closing a signaling loop between opposite transmission directions of said serial link for isolating faults from apparatus connected to said serial channels.

Claim 17

The method of claim 11 further comprising the steps of temporarily storing said data word so as to introduce a predetermined delay said data word comprising the parity bit of the address of said first or second preprogrammed memory means, and comparing said parity bit of said address with the parity bit of a subsequent address of said preprogrammed memory means in order to determine if said counter means is functioning correctly.