US4546401A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Two-pole overcurrent protection device
Assignee: ABB Norden Holding AB
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Filing: 1984-02-08
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Granted: 1985-10-08
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Expires: 2004-02-08
Abstract
Abstract A two-pole overcurrent protection device arranged to interrupt the current flowing in a conductor if the current exceeds a predetermined level employs a semiconductor wafer on which is formed a turn-off thyristor and a MOS transistor. The control electrode of the transistor is supplied with a voltage dependent on the on-state voltage drop of the thyristor and, therefore, on its current, and at a certain thyristor current the transistor short-circuits one of the emitter junctions of the thyristor to extinguish the thyristor. For firing the thyristor, one of the base layers thereof is supplied with a gate trigger current via a JFET transistor portion formed in the semiconductor wafer with a horizontal channel region. This transistor portion is designed so that its saturation current exceeds, with a suitable margin, the current necessary for firing the thyristor. When a high voltage exists across the thyristor, the transistor portion will limit the current flowing to the base layer to a value which is equal to the saturation current of the transistor portion.
Inventors
- 👤 Per Svedberg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:00
CPC Classifications
H; H10; H10D; H10D8/00; H10D8/80; H02; H02H; H02H9/00; H02H9/02; H02H9/025; H10D18/00; H10D18/60; H10D18/65; H10D18/655; H10D89/00; H10D89/60; H10D89/601
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
194 words
A two-pole overcurrent protection device for connection into a current-carrying conductor which device comprises a normally conducting turn-off thyristor having a semiconductor body with, in successive order, a first emitter layer, a first base layer, a second base layer and a second emitter layer, an MOS transistor integrated with the thyristor and connected in parallel with a PN junction of the turn-off thyristor existing between the first emitter layer and the first base layer, which MOS transistor is arranged, when the voltage across the turn-off thyristor exceeds a predetermined value, to short-circuit the said PN junction and cause the turn-off thyristor to cease conducting, characterized in that the said turn-off thyristor is arranged to be supplied with a gate trigger current via a channel region with the same conduction type as the second base layer of the thyristor and arranged adjacent this layer, the channel region being located between a part of the first base layer of the thyristor and a surface of the semiconductor, whereby current through said channel region will flow substantially parallel to said surface and, with an increasing voltage across the thyristor the current through said channel region is limited.
Claim 2
Dependent Claim
194 words
A two-pole overcurrent protection device for connection into a current-carrying conductor which device comprises a normally conducting turn-off thyristor having a semiconductor body with, in successive order, a first emitter layer, a first base layer, a second base layer and a second emitter layer, an MOS transistor integrated with the thyristor and connected in parallel with a PN junction of the turn-off thyristor existing between the first emitter layer and the first base layer, which MOS transistor is arranged, when the voltage across the turn-off thyristor exceeds a predetermined value, to short-circuit the said PN junction and cause the turn-off thyristor to cease conducting, characterized in that the said turn-off thyristor is arranged to be supplied with a gate trigger current via a channel region with the same conduction type as the second base layer of the thyristor and arranged adjacent this layer, the channel region being located between a part of the first base layer of the thyristor and a surface of the semiconductor, whereby current through said channel region will flow substantially parallel to said surface and, with an increasing voltage across the thyristor the current through said channel region is limited.
Claim 3
Dependent Claim
28 words
An overcurrent protection device according to claim 1, in which the region of the opposite conduction type consists of the said first base layer of the turn-off thyristor.
Claim 4
Dependent Claim
60 words
An overcurrent protection device according to claim 1, in which the said first base layer of the turn-off thyristor is provided with an opening through which the second base layer of the turn-off thyristor extends up to the said surface of the semiconductor body, and in which the said channel region is arranged at the edge of the said opening.
Claim 5
Dependent Claim
60 words
An overcurrent protection device according to claim 2, in which the said first base layer of the turn-off thyristor is provided with an opening through which the second base layer of the turn-off thyristor extends up to the said surface of the semiconductor body, and in which the said channel region is arranged at the edge of the said opening.
Claim 6
Dependent Claim
41 words
An overcurrent protection device according to claim 3, in which a conducting layer, electrically connected to the first base layer of the turn-off thyristor is arranged on an electrically insulating layer applied across the said channel region and the said opening.
Claim 7
Dependent Claim
41 words
An overcurrent protection device according to claim 4, in which a conducting layer, electrically connected to the first base layer of the turn-off thyristor is arranged on an electrically insulating layer applied across the said channel region and the said opening.
Claim 8
Dependent Claim
32 words
A bidirectional overcurrent protection device as claimed in claim 1, in which a second MOS transistor and a second channel region are integrated with the turn-off thyristor in the same semiconductor body.
References Cited (Backward Citations)
US3263128A
Cited
US3303360A
Cited
US4224634A
Cited
US4244000A
Cited
US4268846A
Cited
US4331884A
Cited
US4400711A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-10-07 | 1989-04-08 | 1989-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-10-07 | 1993-04-08 | 1993-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-10-07 | 1997-04-08 | 1997-10-08 | $7700.00 | Window Closed / Lapsed |