US4546268A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Narrow pulsewidth pulse generator circuit utilizing NPN microwave transistors
Assignee: United States Department of the Air Force
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Filing: 1983-12-08
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Granted: 1985-10-08
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Expires: 2003-12-08
Abstract
Abstract A pulse generator circuit for providing pulses having pulse widths in the order of one nanosecond. The circuitry utilizes NPN microwave transistors exclusively to achieve this result.
Inventors
- 👤 Stephen P. Caldwell
- 👤 David R. Pedersen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 19:31
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/53; H03K3/57; H03K5/00; H03K5/01; H03K5/04; H03K5/07
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
160 words
A pulse generator circuit comprising: a signal input terminal, a signal output terminal, first, second and third NPN transistors each having a base, an emitter and a collector, means for coupling the base of said first transistor to said input terminal, means for coupling the emitter of said first transistor to a negative voltage terminal, means for coupling the collector of said first transistor to the emitter of said second transistor, means for coupling the base of said second transistor to a first reference voltage point, said second transistor having its collector coupled to the base of said third transistor, an inductor connected between the collector of said second transistor and a first positive voltage terminal, means for coupling the collector of said third transistor to a second positive voltage terminal, means for coupling the emitter of said third transistor to a second reference voltage point, and means for coupling the collector of said third transistor to said output terminal.
Claim 2
Dependent Claim
160 words
A pulse generator circuit comprising: a signal input terminal, a signal output terminal, first, second and third NPN transistors each having a base, an emitter and a collector, means for coupling the base of said first transistor to said input terminal, means for coupling the emitter of said first transistor to a negative voltage terminal, means for coupling the collector of said first transistor to the emitter of said second transistor, means for coupling the base of said second transistor to a first reference voltage point, said second transistor having its collector coupled to the base of said third transistor, an inductor connected between the collector of said second transistor and a first positive voltage terminal, means for coupling the collector of said third transistor to a second positive voltage terminal, means for coupling the emitter of said third transistor to a second reference voltage point, and means for coupling the collector of said third transistor to said output terminal.
Claim 3
Dependent Claim
25 words
Apparatus as defined in claim l and further including a capacitor connected between the collector of said second transistor and said first positive voltage terminal.
Claim 4
Dependent Claim
26 words
Apparatus as defined in claim 2 and further comprising a damping resistor connected between the collector of said second transistor and said first positive voltage terminal.
Claim 5
Dependent Claim
26 words
Apparatus as defined in claim 3 and further comprising a semiconductor diode connected between the collector of said second transistor and said first positive voltage terminal.
Claim 6
Dependent Claim
24 words
Apparatus as defined in claim 4 wherein said means for coupling the collector of said third transistor to said output terminal includes a capacitor.
Claim 7
Dependent Claim
24 words
Apparatus as defined in claim 5 wherein said means for coupling the base of said first transistor to said input terminal includes a transformer.
Claim 8
Dependent Claim
27 words
Apparatus as defined in claim 6 wherein said means for coupling the collector of said third transistor to a second positive voltage terminal includes a second inductor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-10-07 | 1989-04-08 | 1989-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-10-07 | 1993-04-08 | 1993-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-10-07 | 1997-04-08 | 1997-10-08 | $7700.00 | Window Closed / Lapsed |