Patent US4545014A successfully refreshed from Google Patents.
US4545014A
Expired / Lapsed
US
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Information processing apparatus
Assignee: NEC Corp
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Filing: 1981-11-25
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Granted: 1985-10-01
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Expires: 2001-11-25
Abstract
Abstract An information processing apparatus employs first and second direct memory access controllers which cooperate during transfer of information between first and second devices, e.g. memories. The first controller controls information transfer from the first memory to the second controller and the second controller transfers the information from its own internal storage to the second memory while simultaneously receiving further information under the control of the first controller. The second controller includes address control circuitry for high speed generation of non-sequential addresses for writing into the second memory.
Inventors
- 👤 Tetsuji Oguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:50
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/285
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
288 words
An information processing apparatus, comprising: a central processing unit; a first address bus and a first data bus coupled to said central processing unit; a transfer unit having data to be transferred, said transfer unit comprising a first memory coupled to said first address bus and said first data bus; a first controller coupled to said first address bus and said first data bus; a storing unit, said storing unit comprising a second controller having first and second registers, said first register being coupled to said first memory via said first data bus; coupling means for coupling said first register to said second register; a receiver unit for receiving data transferred from said transfer unit, said receiver unit comprising a second memory; a second address bus and a second data bus for coupling said second memory and said second controller, said second register being coupled to said second memory via said second data bus; said first controller comprising means for controlling a data transfer from said first memory to said second memory by providing a first address through said first address bus to said first memory for reading a first data out of said first memory, the read-out first data being stored in said first register via said first data bus, said second controller including means for transferring said first data from said first register to said second register while said first controller transfers a second address to said first memory for reading out a second data; and said second controller further comprising means for transferring said first data from said second register to said second memory via said second data bus while the read-out second data from said first memory is simultaneously stored into said first register.
Claim 2
Dependent Claim
288 words
An information processing apparatus, comprising: a central processing unit; a first address bus and a first data bus coupled to said central processing unit; a transfer unit having data to be transferred, said transfer unit comprising a first memory coupled to said first address bus and said first data bus; a first controller coupled to said first address bus and said first data bus; a storing unit, said storing unit comprising a second controller having first and second registers, said first register being coupled to said first memory via said first data bus; coupling means for coupling said first register to said second register; a receiver unit for receiving data transferred from said transfer unit, said receiver unit comprising a second memory; a second address bus and a second data bus for coupling said second memory and said second controller, said second register being coupled to said second memory via said second data bus; said first controller comprising means for controlling a data transfer from said first memory to said second memory by providing a first address through said first address bus to said first memory for reading a first data out of said first memory, the read-out first data being stored in said first register via said first data bus, said second controller including means for transferring said first data from said first register to said second register while said first controller transfers a second address to said first memory for reading out a second data; and said second controller further comprising means for transferring said first data from said second register to said second memory via said second data bus while the read-out second data from said first memory is simultaneously stored into said first register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-09-30 | 1989-04-01 | 1989-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-09-30 | 1993-04-01 | 1993-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-09-30 | 1997-04-01 | 1997-10-01 | $7700.00 | Window Closed / Lapsed |