US4544853A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated comparator circuit
Assignee: ITT Inc
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Filing: 1983-01-04
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Granted: 1985-10-01
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Expires: 2003-01-04
Abstract
Abstract Between the source of operating voltage (U) and the zero point of the circuit there are provided four series arrangements (s1 . . . s4) of the controlled current paths of each time three insulated-gate field-effect transistors of the same conductivity type, of which the upper transistors (o1 . . . o4) as connected to the source of operating voltage, and the center transistors (m1 . . . m4) are of the depletion type and of identical geometry, while the lower transistors (u1 . . . u4) as connected to the zero point of the circuit, are of the enhancement type and likewise of identical geometry. The center transistors (m1, m3, m4) are connected as a resistors while the gate of the center transistor (m2) is connected to the point connecting the upper and the center transistor (o4, m4). The first input (e1) is connected to the gates of the upper transistors (o1, o3) and the second input (e2) to the gates of the upper transistors (o2, o4). The output of the inverter as formed by the series arrangements (s1 . . . s4) is the point connecting the respective lower and center transistors. The gates of the lower transistors (u2 . . . u4) are each connected to the output of the directly preceding inverter, while the gate of the lower transistor (u1) is connected to the output of its inverter, with the output of the fourth inverter being the output (a) of the comparator circuit.
Inventors
- 👤 Mathew Neal
- 👤 Jochen Reimers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 12:47
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/22; H03K5/24; H03K5/2472; G; G11; G11C; G11C7/00; G11C7/06; G11C7/062
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
309 words
An integrated comparator circuit comprising a plurality of insulated-gate field effect transistors of the same conductivity type, said circuit being responsive to the potential difference between first and second input terminals to provide an output signal at an output terminal, said circuit comprising: a first circuit branch comprising first, second and third transistors having their controlled current paths serially connected between a voltage source and a zero point for said current; a second circuit branch comprising fourth, fifth and sixth transistors having their controlled current paths serially connected between said voltage source and said zero point; a third circuit branch comprising seventh, eighth and ninth transistors having their controlled current paths serially connected between said voltage source and said zero point; a fourth circuit branch comprising tenth, eleventh and twelth transistors having their controlled current paths serially connected between said voltage source and said zero point; the gate of said first transistor and the gate of said seventh transistor both being connected to said first input terminal; the gate of said fourth transistor and the gate of said tenth transistor both being connected to said second input terminal; the gate of said second transistor being coupled to the junction between said first and second transistors; the gate of said eighth transistor being connected to the junction between said seventh and eighth transistors; the gates of said fifth and eleventh transistors both being connected to the junction between said tenth and eleventh transistors; the gates of said third and said sixth transistors being coupled to the junction between said second and third transistors; the gate of said ninth transistor being connected to the junction between said fifth and sixth transistors; the gate of said twelfth transistor being connected to the junction between said eighth and ninth transistors; said output terminal connected to the junction of said eleventh and twelfth transistors.
Claim 2
Dependent Claim
309 words
An integrated comparator circuit comprising a plurality of insulated-gate field effect transistors of the same conductivity type, said circuit being responsive to the potential difference between first and second input terminals to provide an output signal at an output terminal, said circuit comprising: a first circuit branch comprising first, second and third transistors having their controlled current paths serially connected between a voltage source and a zero point for said current; a second circuit branch comprising fourth, fifth and sixth transistors having their controlled current paths serially connected between said voltage source and said zero point; a third circuit branch comprising seventh, eighth and ninth transistors having their controlled current paths serially connected between said voltage source and said zero point; a fourth circuit branch comprising tenth, eleventh and twelth transistors having their controlled current paths serially connected between said voltage source and said zero point; the gate of said first transistor and the gate of said seventh transistor both being connected to said first input terminal; the gate of said fourth transistor and the gate of said tenth transistor both being connected to said second input terminal; the gate of said second transistor being coupled to the junction between said first and second transistors; the gate of said eighth transistor being connected to the junction between said seventh and eighth transistors; the gates of said fifth and eleventh transistors both being connected to the junction between said tenth and eleventh transistors; the gates of said third and said sixth transistors being coupled to the junction between said second and third transistors; the gate of said ninth transistor being connected to the junction between said fifth and sixth transistors; the gate of said twelfth transistor being connected to the junction between said eighth and ninth transistors; said output terminal connected to the junction of said eleventh and twelfth transistors.
Claim 3
Dependent Claim
45 words
A circuit in accordance with claim 1 wherein: said first, fourth, seventh and tenth transistors are of the depletion type; said second, fifth, eighth and eleventh transistors are of the depletion type; and said third, sixth, ninth and twelfth transistors are of the enhancement type.
Claim 4
Dependent Claim
45 words
A circuit in accordance with claim 1 wherein: said first, fourth, seventh and tenth transistors are of identical geometrical dimensions; said second, fifth, eighth and eleventh transistors are of idential geometrical dimensions; and said third, sixth, ninth and twelfth transistors are of identical geometrical dimensions.
Claim 5
Dependent Claim
45 words
A circuit in accordance with claim 2 wherein: said first, fourth, seventh and tenth transistors are of identical geometrical dimensions; said second, fifth, eighth and eleventh transistors are of identical geometrical dimensions; and said third, sixth, ninth and twelfth transistors are of identical geometrical dimensions.
References Cited (Backward Citations)
US4375039A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-09-30 | 1989-04-01 | 1989-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-09-30 | 1993-04-01 | 1993-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-09-30 | 1997-04-01 | 1997-10-01 | $7700.00 | Window Closed / Lapsed |