Offset compensated switched capacitor circuits

Claim 2

A low slew rate switched capacitor system including sampling and reset intervals during each cycle of operation of said system, comprising: an operational amplifier; an input capacitor connected to one input of said operational amplifier; means for receiving a source of input signals to be amplified and applying such signals to said input capacitor; a feedback capacitor connected in circuit between the said one input and the output of said operational amplifier; a compensating capacitor connected in a second circuit between the output of said operational amplifier and said one input to said operational amplifier; and switching circuit means for maintaining the output of the operational amplifier during the reset phase of the cycle close to the output level during the sampling phase of the system switching cycle, said switching circuit means including means for first, connecting said input capacitor to the signal source and said feedback capacitor in circuit from said one input to the output of said integrating amplifier, while isolating said compensating capacitor; and secondly, opening the circuitry from said signal source to said input capacitor, and from said feedback capacitor to said output, while concurrently closing the circuit including said compensating capacitor, and grounding the input to said input capacitor.

Claim 3

A switched capacitor system as defined in claim 1 further comprising additional switching circuit means connected to the other input of said operational amplifier for essentially duplicating the switching circuitry associated with said one input, to thereby compensate for switching circuit transients.

Claim 4

A switched capacitor system as defined in claim 1 including a plurality of additional input capacitors and associated switching circuitry connected essentially in parallel with the input capacitor of claim 1.

Claim 5

A switched capacitor system as defined in claim 3 wherein said input capacitors have values of capacitance which are related to one another by powers of two.

Claim 6

A switched capacitor system as defined in claim 4 wherein switching circuit means are associated with each input capacitor to selectively place it in parallel with the other input capacitors or to isolate it from the other input capacitors.

Claim 7

A switched capacitor system as defined in claim 1 further including switching means for selectively grounding the output side of said feedback capacitor.

Claim 8

A switched capacitor system as defined in claim 1 further including switching means of selectively grounding said compensating capacitor on the side thereof toward said input to said operational amplifier.

Claim 9

A low slew rate switched capacitor digital to analog conversion system including sampling and reset intervals during each cycle of operation of said system, comprising: an operational amplifier; an input capacitor array connected to one input of said operational amplifier; means for receiving an input signal and applying such signal to said input capacitor array; a feedback capacitor connected in circuit between the said one input and the output of said operational amplifier; a compensating capacitor connected in a second circuit between the output of said operational amplifier and said one input to said operational amplifier; switching circuit means for maintaining the output of the operational amplifier during the reset phase of the cycle close to the output level during the sampling phase of the system switching cycle, said switching circuit means including means for first, connecting said input capacitor to the signal source and said feedback capacitor in circuit from said one input to the output of said integrating amplifier, while isolating said compensating capacitor; and secondly, opening the circuitry from said signal source to said input capacitor, and from said feedback capacitor to said output, while concurrently closing the circuit including said compensating capacitor, and grounding the input to said input capacitor; and said input capacitor array including a plurality of parallel input capacitors, with the capacitors having capacitance values related to one another by powers of two, and associated switching circuitry for selectively either isolating individual input capacitors or placing them in parallel circuit relationship with the other input capacitors; whereby the output from said operational amplifier is an analog representation of a digital signal indicated by the array of parallel input capacitors.

Claim 10

A low slew rate switched capacitor digital to analog conversion system including sampling and reset intervals during each cycle of operation of said system, comprising: an operational amplifier; an input capacitor array connected to one input of said operational amplifier; means for receiving an input signal and applying such signal to said input capacitor array; a feedback capacitor connected in circuit between the said one input and the output of said operational amplifier; a compensating capacitor connected in a second circuit between the output of said operational amplifier and said one input to said operational amplifier; switching circuit means for maintaining the output of the operational amplifier during the reset phase of the cycle close to the output level during the sampling phase of the system switching cycle, said switching circuit means including means for first, connecting said input capacitor to the signal source and said feedback capacitor in circuit from said one input to the output of said integrating amplifier, while isolating said compensating capacitor; and secondly, opening the circuitry from said signal source to said input capacitor, and from said feedback capacitor to said output, while concurrently closing the circuit including said compensating capacitor, and grounding the input to said input capacitor; and said input capacitor array including a plurality of parallel input capacitors, with the capacitors having capacitance values related to one another by powers of two, and associated switching circuitry for selectively either isolating individual input capacitors or placing them in parallel circuit relationship with the other input capacitors; whereby the output from said operational amplifier is an analog representation of a digital signal indicated by the array of parallel input capacitors.

Claim 11

A switched capacitor system as defined in claim 8 further including switching means for selectively grounding the output side of said feedback capacitor.

Claim 12

A switched capacitor system as defined in claim 7 further including switching means for selectively grounding said compensating capacitor on the side thereof toward said input to said operational amplifier.

Claim 13

A low slew rate switched capacitor system including sampling and reset intervals during each cycle of operation of said system, comprising: an operational amplifier; an input capacitor connected to the inverting input of said operational amplifier; means for receiving a source of input signals to be amplified and applying such signals to said input capacitor; a feedback capacitor connected in circuit between said inverting input and the output of said operational amplifier; a compensating capacitor connected in a second circuit between the output of said operational amplifier and said inverting input to said operational amplifier; and switching circuit means for maintaining the output of the operational amplifier during the reset phase of the cycle close to the output level during the sampling phase of the system switching cycle, said switching circuit means including means for sampling said input signals, and for alternately switching said feedback capacitor and said compensating capacitor in circuit between inverting input and the output of said operational amplifier.

Claim 14

A low slew rate switched capacitor system including sampling and reset intervals during each cycle of operation of said system, comprising: an operational amplifier; an input capacitor connected to the inverting input of said operational amplifier; means for receiving a source of input signals to be amplified and applying such signals to said input capacitor; a feedback capacitor connected in circuit between said inverting input and the output of said operational amplifier; a compensating capacitor connected in a second circuit between the output of said operational amplifier and said inverting input to said operational amplifier; and switching circuit means for maintaining the output of the operational amplifier during the reset phase of the cycle close to the output level during the sampling phase of the system switching cycle, said switching circuit means including means for sampling said input signals, and for alternately switching said feedback capacitor and said compensating capacitor in circuit between inverting input and the output of said operational amplifier.

Claim 15

A switched capacitor system as defined in claim 11 further comprising additional switching circuit means connected to the other input of said operational amplifier for essentially duplicating the switching circuitry associated with said one input, to thereby compensate for switching circuit transients.

Claim 16

A switched capacitor system as defined in claim 11 including a plurality of additional input capacitors and associated switching circuitry connected essentially in parallel with the input capacitor of claim 1.

Claim 17

A switched capacitor system as defined in claim 13 wherein said input capacitors have values of capacitance which are related to one another by powers of two.

Claim 18

A switched capacitor system as defined in claim 14 wherein switching circuit means are associated with each input capacitor to selectively place it in parallel with the other input capacitors or to isolate it from the other input capacitors.

Claim 19

A system as defined in claim 1 wherein said one input of said operational amplifier is the inverting input thereof.

Claim 20

A system as defined in claim 8 wherein said one input of said operational amplifier is the inverting input thereof.