Patent US4543066A successfully refreshed from Google Patents.
US4543066A
Expired / Lapsed
US
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Digital transmitter simulator
Assignee: United States Department of the Navy
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Filing: 1984-03-30
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Granted: 1985-09-24
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Expires: 2004-03-30
Abstract
Abstract A modulated VLF signal source has the capability for providing radio sign suitable for performance testing and operator training relative to VLF digital data receiving systems. A number of separately proven components are utilized to implement a relatively low cost, reliable compact and easily transportable system. A digital modulator is driven through suitably adapted microprocessor circuits by selective information stored on floppy diskettes. Operator input commands actuate the modulator to generate representations of data in the continuous shift keying, frequency shift keying, or minimum shift keying output modes to provide a modulated VLF output which can be received by several receive systems. Prolonged data transmissions can be produced by merely selecting the appropriate floppy diskettes to initiate the desired modulated sequences.
Inventors
- 👤 Donald M. French
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 03:32
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/0008; G; G09; G09B; G09B9/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
278 words
A digital transmit simulator for generating shift key modulated very low frequency signals for performance testing of at least one receiver comprising: means in the form of at least one readily changeable floppy disk for storing digital data representative of a modulation sequence and modulation mode used to test the receiver; means coupled to the digital data storing means for translating the stored digital data to compatible digital data modulation sequence signals and digital data modulation mode signals; means for providing inputs from a frequency standard for synchronization purposes; means coupled to the frequency standard providing means, the receiver and the translating means for generating shift keying modulated signals, the generating means including a modulator having a plurality of modulation modes coupled to the receiver, a mode register coupled to receive the translated digital data modulation mode signals from the translating means to create a selected actuation signal to initiate the modulator in a particular modulation mode and a data transition circuit coupled to the modulator to provide updated digital data to the translated data modulation sequence signals, the transition circuit including a static RAM having an operating instruction section responsive to operating instructions received from the translating means to provide actuating signals and an A memory and a B memory each responsive to information signals from the translating means to be alternately enabled to pass the information signals to the modulator and the data transition circuit also includes a universal shift register interposed between the static RAM and the modulator for feeding the information signals alternately from the A and B memories in a timed sequence according to a data clock rate signal coming from the modulator.
Claim 2
Dependent Claim
278 words
A digital transmit simulator for generating shift key modulated very low frequency signals for performance testing of at least one receiver comprising: means in the form of at least one readily changeable floppy disk for storing digital data representative of a modulation sequence and modulation mode used to test the receiver; means coupled to the digital data storing means for translating the stored digital data to compatible digital data modulation sequence signals and digital data modulation mode signals; means for providing inputs from a frequency standard for synchronization purposes; means coupled to the frequency standard providing means, the receiver and the translating means for generating shift keying modulated signals, the generating means including a modulator having a plurality of modulation modes coupled to the receiver, a mode register coupled to receive the translated digital data modulation mode signals from the translating means to create a selected actuation signal to initiate the modulator in a particular modulation mode and a data transition circuit coupled to the modulator to provide updated digital data to the translated data modulation sequence signals, the transition circuit including a static RAM having an operating instruction section responsive to operating instructions received from the translating means to provide actuating signals and an A memory and a B memory each responsive to information signals from the translating means to be alternately enabled to pass the information signals to the modulator and the data transition circuit also includes a universal shift register interposed between the static RAM and the modulator for feeding the information signals alternately from the A and B memories in a timed sequence according to a data clock rate signal coming from the modulator.
Claim 3
Dependent Claim
60 words
A digital transmit simulator according to claim 1 in which the data transition circuit further includes a byte ready flip-flop circuit coupled to a microprocessor to optionally enable the microprocessor to obtain a byte of information for transfer from the static RAM to the shift register to transfer the information signals appropriately in the playback mode or record mode, respectively.
Claim 4
Dependent Claim
63 words
A digital transmit simulator according to claim 2 in which the transition circuit further includes a data ready flip-flop circuit coupled to the microprocessor and to the translating means to provide an indication when data is ready to be alternately transferred from the A memory or B memory to the translating means in the record mode and vice versa in the playback mode.
Claim 5
Dependent Claim
46 words
A digital transmit simulator according to claim 3 in which the transition circuit further includes an external status register coupled to the modulator, the data ready flip-flop and the translating means via an external bus to provide an indication of the status of the transition circuit.
Claim 6
Dependent Claim
43 words
A digital transmit simulator according to claim 4 in which the transition circuit further includes a minute and second flip-flop circuit coupled to the frequency standard providing means the translating means and the external status register to assure a proper synchronized actuation thereof.
Claim 7
Dependent Claim
49 words
A digital transmit simulator according to claim 5 in which the transition circuit further includes a reset-and-hold circuit coupled to the data ready flip-flop, the modulator, the microprocessor and the minute and second flip-flop circuit to allow the transition circuit to be reset and started at an appropriate time.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-09-23 | 1989-03-25 | 1989-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-09-23 | 1993-03-25 | 1993-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-09-23 | 1997-03-25 | 1997-09-24 | $7700.00 | Window Closed / Lapsed |