Patent US4538240A successfully refreshed from Google Patents.
US4538240A
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Method and apparatus for performing hashing operations using Galois field multiplication
Assignee: International Business Machines Corp
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Filing: 1982-12-30
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Granted: 1985-08-27
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Expires: 2002-12-30
Abstract
Abstract The invention comprises a method and apparatus for performing a hashing operation on an N bit number under control of a prespecified N bit hashing constant which comprises performing N/K finite field partial multiplications of the object to be hashed by the hashing constant, utilizing K logic and combinatorial circuits all of which operate in parallel to completely evaluate the number in N/K operations. Another feature of the present invention is that the hashing constant loaded into the system may be changed at will with a resultant changing of the hashing characteristics to suit a particular class of objects to be hashed. This is done by a "select" operation. In the "select" operation, the hashing constant is sequentially loaded into said K logic and combinatorial circuits, each of which comprises a feedback shift register (FSR), said feedback shift registers being so configured that at the end of K operational sequences each of said feedback shift registers contains said hashing constant shifted and permuted in accordance with the particular feedback configuration of said register, a number of bits proportional to its location in the sequence of feedback shift registers, such that the hashing constant in the shift register FSR i will be shifted in a predetermined direction (i-1) N/K bit positions. Each of the operational sequences referred to above comprises a hashing sequence which includes N/K shifts of the feedback shift registers.
Inventors
- 👤 John L. Carter
- 👤 George Markowsky
- 👤 Mark N. Wegman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:12
CPC Classifications
G; G06; G06F; G06F16/00; G06F16/90; G06F16/901; G06F16/9014
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
176 words
A hashing generator for performing a hashing operation on an N bit operand as a function of a predetermined N bit hashing constant, said generator comprising a shift register for receiving the operand to be hashed, a register for receiving and storing the hashing constant, K feedback shift registers wherein K is an integer factor of N, means for loading each of said K feedback shift registers with said hasing constant shifted from the low to the high order direction N/K-bit positions with respect to each of its adjacent feedback shift registers, means including a result register and combinatorial circuit means for accumulating the contents of each of said K feedback shift registers as a function of the binary state of an associated bit in said operand shift register together with the results of the immediately preceding accumulation and means for sequentially shifting all of said K feedback shift registers and said operand shift register and successively accumulating the interim results in said result register a total of N/K times to perform a complete hashing operation.
Claim 2
Dependent Claim
176 words
A hashing generator for performing a hashing operation on an N bit operand as a function of a predetermined N bit hashing constant, said generator comprising a shift register for receiving the operand to be hashed, a register for receiving and storing the hashing constant, K feedback shift registers wherein K is an integer factor of N, means for loading each of said K feedback shift registers with said hasing constant shifted from the low to the high order direction N/K-bit positions with respect to each of its adjacent feedback shift registers, means including a result register and combinatorial circuit means for accumulating the contents of each of said K feedback shift registers as a function of the binary state of an associated bit in said operand shift register together with the results of the immediately preceding accumulation and means for sequentially shifting all of said K feedback shift registers and said operand shift register and successively accumulating the interim results in said result register a total of N/K times to perform a complete hashing operation.
Claim 3
Dependent Claim
62 words
A hashing generator as set forth in claim 1 wherein the i-th feedback shift register has its output accumulated as a function of the state of the (i-1)×N/K bit position of said operand shift register and means for sequentially shifting said operand shift register so that the contents therein are shifted in a direction from the high to low order bit positions.
Claim 4
Dependent Claim
83 words
A hashing generator as set forth n claim 2 wherein the combinatorial circuit means for combining the current values in the feedback shift registers includes K N-bit AND gates or equivalent circuitry each of which is controlled by the state of an associated bit of the operand shift register, and a (K+1) input parity block, the output of all of siad K AND gates forming K inputs to said parity block wherein the (K+1)-th input comprises the current state of said accumulation means.
Claim 5
Dependent Claim
87 words
A hashing generator as set forth in claim 3 including means operable during a "select" mode of operation of the hashing generator for preloading the K feedback shift registers which includes means for gating the complete contents of the hashing constant register into the first feedback shift register and the contents of the i-th feedback shift register into the (i+1)-th feedback shift register and for selectively causing each of said K feedback shift registers to shift N/K bit positions with respect to its adjacent feedback shift register.
Claim 6
Dependent Claim
48 words
A hashing generator as set forth in claim 4 including means for introducing a predetermined hashing constant into the hashing constant register and for performing said "select" operation whereby the hashing generator will produce a different distribution of output values as a functioning of a different hashing constant.
Claim 7
Dependent Claim
83 words
A hashing generator as set forth in claim 5 wherein each of said feedback shift registers comprises bits designated 0, 1, 2 . . . N-1 and means for shifting the i-th bit into the (i+1)-th bit position and also exclusive-ORing the bit in position N-1 into those bit positions which represent the coefficient of an irreducible polymonial of degree N which have a non-zero value except for bit position 0, and shifting the bit in position N-1 directly into bit position 0.
Claim 8
Dependent Claim
209 words
A hashing generator for performing a hashing operation on an N bit operand as a function of a predetermined N bit hashing constant, said generator comprising a shift register for receiving the operand to be hashed, a register for receiving and storing the hashing constant, K feedback shift registers wherein K is not an integer factor of N, means for loading each of said K feedback shift registers with said hashing constant shifted from the low to the higher order direction L bit positions with respect to each of its adjacent feecback shift registers where L is the greatest integer less than N/K, means for loading a zero into the high order bit position of the operand shift register each time a shift is performed, means including a result register and combinatorial circuit means for accumulating the contents of each of said K feedback shift registers as a function of the binary state of an associated bit in said operand shift register together with the results of the immediately preceding accumulation and means for sequentially shifting all of said K feedback shift registers and said operand shift register and successively accumulating the interim results in said result register a total of L times to perform a complete hashing operation.
Claim 9
Dependent Claim
209 words
A hashing generator for performing a hashing operation on an N bit operand as a function of a predetermined N bit hashing constant, said generator comprising a shift register for receiving the operand to be hashed, a register for receiving and storing the hashing constant, K feedback shift registers wherein K is not an integer factor of N, means for loading each of said K feedback shift registers with said hashing constant shifted from the low to the higher order direction L bit positions with respect to each of its adjacent feecback shift registers where L is the greatest integer less than N/K, means for loading a zero into the high order bit position of the operand shift register each time a shift is performed, means including a result register and combinatorial circuit means for accumulating the contents of each of said K feedback shift registers as a function of the binary state of an associated bit in said operand shift register together with the results of the immediately preceding accumulation and means for sequentially shifting all of said K feedback shift registers and said operand shift register and successively accumulating the interim results in said result register a total of L times to perform a complete hashing operation.
Claim 10
Dependent Claim
86 words
A hashing generator as set forth in claim 7 including means operable during a "select" mode of operation of the hashing generator for preloading the K feedback shift registers which includes means for gating the complete contents of the hashing constant register into the first feedback shift register and the contents of the i-th feedback shift register into the (i+1)-th feedback shift register and for selectively causing each of said feedback shift registers to shift L bit positions with respect to its adjacent feedback shift register.
Claim 11
Dependent Claim
83 words
A hashing generator as set forth in claim 8 wherein each of said feedback shift registers comprises bits designated 0, 1, 2 . . . N-1 and means for shifting the i-th bit into the (i+1)-th bit position and also exclusive-ORing the bit in position N-1 into those bit positions which represent the coefficient of an irreducible polymonial of degree N which have a non-zero value except for bit position 0, and shifting the bit in position N-1 directly into bit position 0.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-08-26 | 1989-02-25 | 1989-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-08-26 | 1993-02-25 | 1993-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-08-26 | 1997-02-25 | 1997-08-27 | $7700.00 | Window Closed / Lapsed |