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US4536664A Expired / Lapsed US ⏱️ 0.0 years remaining

A high speed, non-inverting circuit for providing an interface between TTL logic gates and Schottky transistor logic gates

Assignee: Texas Instruments Inc
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Filing: 1983-02-16
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Granted: 1985-08-20
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Expires: 2003-02-16
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Abstract

Abstract A high speed, noninverting circuit for providing an interface between transistor-transistor logic gates and Schottky transistor logic gates. In one embodiment the output of a TTL circuit is coupled through a Schottky diode to an emitter-follower whose input is Schottky clamped. The output of the emitter-follower is coupled to a constant current sink and to the cathode of a low barrier Schottky diode, the anode of which forms the STL-compatible output of the interface circuit. The present circuit thus performs a noninverting level translation with minimum propagation delay.

Inventors

  • 👤 Robert C. Martin

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 07:19
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/018; H03K19/01806

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 189 words
A circuit for translating a first logic voltage to a second logic voltage for operative connection to a source of potential, comprising: a first high barrier Schottky diode having a cathode to serve as the circuit input, an emitter-follower transistor circuit having an input coupled to the anode of said input Schottky diode, a second high barrier Schottky diode having an anode coupled to the input of said emitter-follower transistor circuit, and a plurality of series-connected diodes, the first of said series-connected diodes having an anode coupled to the cathode of said high barrier Schottky diode and the last of said series-connected diodes having a cathode coupled to ground wherein said input of said emitter-follower transistor circuit is clamped to a voltage level substantially equal to the difference between said first logic voltage and the voltage across said first Schottky diode by said series-connected diodes and said second Schottky diode; a low barrier Schottky diode coupled to receive an output from said emitter follower transistor to serve as an output for the circuit; and a constant current source coupled to said low barrier Schottky to sink the current therethrough.
Claim 2
Dependent Claim 189 words
A circuit for translating a first logic voltage to a second logic voltage for operative connection to a source of potential, comprising: a first high barrier Schottky diode having a cathode to serve as the circuit input, an emitter-follower transistor circuit having an input coupled to the anode of said input Schottky diode, a second high barrier Schottky diode having an anode coupled to the input of said emitter-follower transistor circuit, and a plurality of series-connected diodes, the first of said series-connected diodes having an anode coupled to the cathode of said high barrier Schottky diode and the last of said series-connected diodes having a cathode coupled to ground wherein said input of said emitter-follower transistor circuit is clamped to a voltage level substantially equal to the difference between said first logic voltage and the voltage across said first Schottky diode by said series-connected diodes and said second Schottky diode; a low barrier Schottky diode coupled to receive an output from said emitter follower transistor to serve as an output for the circuit; and a constant current source coupled to said low barrier Schottky to sink the current therethrough.
Claim 3
Dependent Claim 41 words
The circuit of claim 1 wherein said low barrier Schottky diode has a cathode coupled to the output of said emitter-follower transistor circuit wherein the anode of said low barrier Schottky diode comprises the output of said logic voltage translating circuit.
Claim 4
Dependent Claim 77 words
The circuit of claim 2 wherein said constant current source comprises: a first Schottky clamped transistor having a collector coupled to said emitter-follower transistor circuit output and to a cathode of said low barrier Schottky diode, and an emitter coupled to ground; and a second transistor having a collector coupled to its base and to the base of said first Schottky clamped transistor, a collector coupled to a source of potential and an emitter coupled to ground.
Claim 5
Dependent Claim 53 words
The circuit of claim 3 wherein said second Schottky diode and the input of said emitter-follower transistor circuit are coupled to a first logic voltage supply, said emitter-follower transistor circuit having at least one collector which with said second transistor of said constant current source are coupled to a second logic voltage supply.
Claim 6
Dependent Claim 46 words
The circuit of claim 1 further comprising a plurality of Schottky diodes, each having a cathode coupled to the output of said emitter-follower transistor circuit wherein the anode of each of said plurality of Schottky diodes comprises an independent output of said logic voltage translating circuit.
Claim 7
Dependent Claim 78 words
The circuit of claim 5 wherein said constant current source comprises: a first Schottky clamped transistor having a collector coupled to said emitter-follower transistor circuit output and to the cathodes of said plurality of output Schottky diodes, and an emitter coupled to ground; and a second transistor having a collector coupled to its base and to the base of said first Schottky clamped transistor, a collector coupled to a source of potential, and an emitter coupled to ground.
Claim 8
Dependent Claim 54 words
The circuit of claim 6 wherein said second Schottky diode and the input of said emitter-follower transistor circuit are coupled to a first logic voltage supply, and said emitter-follower transistor circuit having at least one collector which with said second transistor of said constant current source are coupled to a second logic voltage supply.

References Cited (Backward Citations)

US3439186A Cited
US3491251A Cited
US3553486A Cited
US3979611A Cited
US4129790A Cited
US4405870A Cited
US4458162A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-08-19 1989-02-18 1989-08-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-08-19 1993-02-18 1993-08-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-08-19 1997-02-18 1997-08-20 $7700.00 Window Closed / Lapsed

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