Recording channel with signal controlled integrated analog circuits

Claim 2

A recording channel for a data storage file including means for converting the signal in the read transducer to a binary digital signal having a value which corresponds to the value of stored data that produced said signal, said converting means comprising: a plurality of integrated circuits including (1) a read amplifier having its input connected to said read transducer; (2) a peak detector including an input terminal, a first set of interconnected analog circuits and a digital output circuit to provide said binary digital signal, and at least one control terminal for each of said circuits of said peak detector to permit the adjustment of an operating parameter of each said circuit of said peak detector in accordance with a control signal supplied to said at least one control terminal; and (3) circuit means including (a) a second set of analog circuits connected betwen said read amplifier and said input terminal of said peak detector to (i) maintain the amplitude of said signal supplied to said peak detector at a predetermined amplitude independent of the output of said read amplifier; and (ii) eliminate any DC component present in the signal supplied from said read amplifier; and (b) means for dynamically and continuously adjusting preselected parameters of said second set of analog circuits, including means for developing control signals for said second set of analog circuits in accordance with the signal supplied to said peak detector.

Claim 3

The recording channel set forth in claim 1 in which said data storage file is a magnetic disk file, said transducer is a magnetic transducer having a read element, and said read amplifier has an adjustable gain.

Claim 4

The recording channel set forth in claim 1 in which said second set of analog circuits includes a summing junction having a first input terminal connected to the output of said read amplifier and a second input terminal connected to said means for developing control signals.

Claim 5

The recording channel set forth in claim 3 in which said second set of analog circuits further includes a variable gain amplifier having an input terminal coupled to receive the output signal from said summing junction and a gain control terminal connected to said means for developing control signals.

Claim 6

The recording channel set forth in claim 3 in which said means for developing control signals includes a first counter/register, a first digital to analog converter connected between said first counter/register and said second input terminal of said summing junction, first means for selectively incrementing or decrementing said first counter/register in response to first clock signals and a counter direction control signal.

Claim 7

The combination recited in claim 5 in which said first means for selectively incrementing or decrementing said first counter/register includes an offset detector connected in a feedback loop which extends from the output of said second set of analog circuits to said means for developing control signals to control the count direction of said first counter/register so as to reduce the zero any DC component in the signal supplied to said peak detector from said second set of analog circuits.

Claim 8

The recording channel set forth in claim 5 in which said means for developing control signals includes a second counter/register, a second digital to analog converter connected between said second counter/register and said gain control terminal of said variable gain amplifier and second means for selectively incrementing or decrementing said second counter/register in response to second clock signals and a second counter direction control signal.

Claim 9

The combination recited in claim 7 in which said second means for selectively incrementing or decrementing said counter/register includes a signal magnitude detector connected in a feedback path which extends from the output of said second set of analog circuits to said means for developing control signals to control the counter direction of said second counter/register so as to maintain the amplitude of the signal supplied to said peak detector from said second set of analog circuits at a predetermined value substantially independent of the value of the signal from said read amplifier.

Claim 10

The recording channel set forth in claim 1 in which said second set of analog circuits includes a summing junction and a variable gain amplifier, said summing junction having a first input terminal connected to the output of said read amplifier and a second control input terminal and an output terminal connected to the input of said variable gain amplifier, said variable gain amplifier having a control signal input terminal and means connecting said control input terminals to said means for developing control signals.

Claim 11

The recording channel set forth in claim 9 in which said means for developing control signals comprises: (1) first means for supplying to said summing junction a first control signal, the value of which tends to reduce to zero any DC component in the signal supplied from said read amplifier; and (2) second means for supplying to said variable gain amplifier a second control signal, the value of which tends to maintain the amplitude of the signal supplied to said peak detector at a predetermined value.

Claim 12

The recording channel set forth in claim 10 in which said first and second means for supplying each include a counter/register and an analog to digital converter.

Claim 13

The recording channel set forth in claim 1 in which said means for adjusting comprises a register or counter and a digital to analog converter associated with each said analog circuit of said second set of analog circuits.

Claim 14

The recording channel set forth in claim 12 further including a microcontroller and an address/data bus interconnecting said microcontroller to each said register and counter.

Claim 15

A recording channel for a data storage file including means for converting the signal in the read transducer to a binary digital signal having a value which corresponds to the value of stored data that produced said signal, said converting means comprising: a plurality of integrated circuits including (1) a read amplifier having its input connected to said read transducer; (2) a peak detector including an input terminal, a first set of interconnected analog circuits and a digital output circuits to provide said binary digital signal, and at least one control terminal for each of said circuits of said peak detector to permit the adjustment of an operating parameter of each said circuit of said peak detector in accordance with a control signal supplied to said at least one control terminal; and (3) circuit means including (a) a second set of analog circuits connected between said read amplifier and said input terminal of said peak detector to (i) maintain the amplitude of said signal supplied to said peak detector at a predetermined amplitude independent of the output of said read amplifier; and (ii) eliminate any DC component present in the signal supplied from said read amplifier; and (b) means for adjusting preselected parameters of said second set of analog circuits, including means for developing control signals for said second set of analog circuits in accordance with the signal supplied to said peak detector, and further including a summing junction having a first input terminal connected to the output of said read amplifier and a second input terminal connected to said means for developing control signals.

Claim 16

A recording channel for a data storage file including means for converting the signal in the read transducer to a binary digital signal having a value which corresponds to the value of stored data that produced said signal, said converting means comprising: a plurality of integrated circuits including (1) a read amplifier having its input connected to said read transducer; (2) a peak detector including an input terminal, a first set of interconnected analog circuits and a digital output circuits to provide said binary digital signal, and at least one control terminal for each of said circuits of said peak detector to permit the adjustment of an operating parameter of each said circuit of said peak detector in accordance with a control signal supplied to said at least one control terminal; and (3) circuit means including (a) a second set of analog circuits connected between said read amplifier and said input terminal of said peak detector to (i) maintain the amplitude of said signal supplied to said peak detector at a predetermined amplitude independent of the output of said read amplifier; and (ii) eliminate any DC component present in the signal supplied from said read amplifier; and (b) means for adjusting preselected parameters of said second set of analog circuits, including means for developing control signals for said second set of analog circuits in accordance with the signal supplied to said peak detector, and further including a summing junction having a first input terminal connected to the output of said read amplifier and a second input terminal connected to said means for developing control signals.