Patent US4534028A successfully refreshed from Google Patents.
US4534028A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Random testing using scan path technique
Assignee: Siemens Corporate Research and Support Inc
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Filing: 1983-12-01
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Granted: 1985-08-06
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Expires: 2003-12-01
Abstract
Abstract A method is disclosed for testing a complex digital circuit that is designed as a serial access scan path. The circuit incorporates a number of flip-flops, at least some of which are selectively connectable into a scan path shift register. The circuit also has a number of primary inputs, primary outputs, a scan path input and a scan path output. In the testing method, a first digital test pattern is applied to the primary inputs and a second digital test pattern is shifted into the scan path shift register. The digits appearing at the primary outputs are repeatedly compared with those of a first digital number indicative of the proper operation of the circuit as each digit of the second digital test pattern is shifted into the scan path shift register. If the digits appearing at the primary outputs are not equal to those of the digital numbers to which they are compared, a signal indicative of faulty circuit operation is produced.
Inventors
- 👤 Erwin Trischler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:57
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318566
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
268 words
A method of testing a complex digital circuit designed as a serial access scan path and comprising: (a) a plurality of primary inputs; (b) a plurality of primary outputs; (c) a plurality of flip-flops, some of which are selectively connectable into a scan path shift register; (d) a scan path input connected to one end of said shift register; and (e) a scan path output connected to the opposite end of said shift register, said method comprising the steps of: (1) forming said scan path shift register in said circuit; (2) clearing said scan path shift register; (3) applying a first digital test pattern to said primary inputs; (4) shifting the first digit of a second digital test pattern into said scan path shift register via said scan path input; (5) comparing the digits appearing at said primary outputs with those of a first digital number indicative of the proper operation of said circuit; (6) shifting the next digit of said second digital test pattern into said scan path shift register via said scan path input; (7) comparing the digits appearing at said primary outputs with those of another digital number indicative of the proper operation of said circuit; (8) repeating steps (6) and (7) for each successive digit of said second test pattern until all of the stages of said scan path shift register have been filled by digits of said second digital test pattern; and (9) producing a signal indicative of faulty circuit operation if the digits appearing at said primary outputs are not equal to those of the digital numbers to which they are compared.
Claim 2
Independent Claim
268 words
A method of testing a complex digital circuit designed as a serial access scan path and comprising: (a) a plurality of primary inputs; (b) a plurality of primary outputs; (c) a plurality of flip-flops, some of which are selectively connectable into a scan path shift register; (d) a scan path input connected to one end of said shift register; and (e) a scan path output connected to the opposite end of said shift register, said method comprising the steps of: (1) forming said scan path shift register in said circuit; (2) clearing said scan path shift register; (3) applying a first digital test pattern to said primary inputs; (4) shifting the first digit of a second digital test pattern into said scan path shift register via said scan path input; (5) comparing the digits appearing at said primary outputs with those of a first digital number indicative of the proper operation of said circuit; (6) shifting the next digit of said second digital test pattern into said scan path shift register via said scan path input; (7) comparing the digits appearing at said primary outputs with those of another digital number indicative of the proper operation of said circuit; (8) repeating steps (6) and (7) for each successive digit of said second test pattern until all of the stages of said scan path shift register have been filled by digits of said second digital test pattern; and (9) producing a signal indicative of faulty circuit operation if the digits appearing at said primary outputs are not equal to those of the digital numbers to which they are compared.
Claim 3
Dependent Claim
81 words
The method defined in claim 1, further comprising the steps of: (10) operating said circuit for at least one clock cycle in its normal operating mode; (11) comparing the digits appearing at said primary outputs with those of another digital number indicative of the proper operation of said circuit; and (12) producing a signal indicative of faulty circuit operation if the digits appearing at said primary outputs are not equal to those of the digital number to which they are compared.
Claim 4
Dependent Claim
84 words
The method defined in claim 2, further comprising the steps of shifting the contents of said scan path shift register to a second shift register via said scan path output; comparing the respective digits stored in said second shift register with the digits of a third digital number indicative of the proper operation of said circuit; and producing a signal indicative of faulty circuit operation if the digits stored in said second shift register are not equal to those of said third digital number.
Claim 5
Dependent Claim
20 words
The method defined in claim 2, wherein said circuit is operated in step (10) for a plurality of clock cycles.
Claim 6
Dependent Claim
67 words
The method defined in claim 4, wherein the number of said clock cycles is determined as follows: (1) testing the circuit with one clock cycle and noting the fault coverage; (2) repeating step (1) with an additional clock cycle until the fault coverage ceases to increase substantially, thereby to optimize the number of clock cycles between the increase in fault coverage and the increase in testing cost.
References Cited (Backward Citations)
US3376695A
Cited
DE2111493A1
Cited
US4423509A
Cited
US4298980A
Cited
US4340857A
Cited
US4493077A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-08-05 | 1989-02-04 | 1989-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-08-05 | 1993-02-04 | 1993-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-08-05 | 1997-02-04 | 1997-08-06 | $7700.00 | Window Closed / Lapsed |